// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.10.3.144
// Netlist written on Wed Sep 14 20:20:07 2022
//
// Verilog Description of module top
//

module top (clk, led, pwma, pwmb, tx, rx) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(1[8:11])
    input clk;   // f:/home/mini-step-fpga/prj/h_brige/top.v(3[8:11])
    output led;   // f:/home/mini-step-fpga/prj/h_brige/top.v(5[9:12])
    output pwma;   // f:/home/mini-step-fpga/prj/h_brige/top.v(7[9:13])
    output pwmb;   // f:/home/mini-step-fpga/prj/h_brige/top.v(8[9:13])
    output tx;   // f:/home/mini-step-fpga/prj/h_brige/top.v(10[9:11])
    input rx;   // f:/home/mini-step-fpga/prj/h_brige/top.v(11[8:10])
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(3[8:11])
    
    wire GND_net, VCC_net, led_c, pwma_c, pwmb_c, tx_c, rx_c, 
        rst_n;
    wire [7:0]cmd;   // f:/home/mini-step-fpga/prj/h_brige/top.v(18[19:22])
    
    wire wr;
    wire [31:0]wr_data;   // f:/home/mini-step-fpga/prj/h_brige/top.v(20[12:19])
    wire [31:0]cmd_data;   // f:/home/mini-step-fpga/prj/h_brige/top.v(21[13:21])
    
    wire valid_o;
    wire [2:0]led_status;   // f:/home/mini-step-fpga/prj/h_brige/top.v(25[11:21])
    wire [31:0]cr;   // f:/home/mini-step-fpga/prj/h_brige/top.v(37[12:14])
    wire [31:0]tcr;   // f:/home/mini-step-fpga/prj/h_brige/top.v(37[17:20])
    wire [31:0]hcr;   // f:/home/mini-step-fpga/prj/h_brige/top.v(37[23:26])
    
    wire clk_c_enable_103, n4632, n4631, n4332, n992, n991, n990, 
        n989, n988, n987, n986, n985, n984, n982, n983, n15, 
        ope, n14, n4627, n4932, n1012, n1011, n1010, n1009, 
        n1008, n1007, n1006, n1005, n1004, n1003, n981, n993, 
        n994, n995, n996, n997, n998, n999, n1002, n1001, n1000, 
        clk_c_enable_296, clk_c_enable_45, clk_c_enable_147, clk_c_enable_265, 
        clk_c_enable_216, n4619, clk_c_enable_225;
    
    LUT4 i2259_2_lut (.A(cmd_data[1]), .B(n15), .Z(n1011)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2259_2_lut.init = 16'h8888;
    LUT4 i1_2_lut_rep_57 (.A(valid_o), .B(n14), .Z(n4627)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam i1_2_lut_rep_57.init = 16'h2222;
    LUT4 i2202_2_lut (.A(cmd_data[0]), .B(n15), .Z(n1012)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2202_2_lut.init = 16'h8888;
    LUT4 i2260_2_lut (.A(cmd_data[2]), .B(n15), .Z(n1010)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2260_2_lut.init = 16'h8888;
    FD1P3IX led_status__i0 (.D(cmd_data[0]), .SP(clk_c_enable_45), .CD(n4632), 
            .CK(clk_c), .Q(led_status[0]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam led_status__i0.GSR = "DISABLED";
    LUT4 i2261_2_lut (.A(cmd_data[3]), .B(n15), .Z(n1009)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2261_2_lut.init = 16'h8888;
    LUT4 i3_4_lut (.A(cmd[0]), .B(n14), .C(n4631), .D(cmd[1]), .Z(n15)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(66[5:9])
    defparam i3_4_lut.init = 16'hfffe;
    IB rx_pad (.I(rx), .O(rx_c));   // f:/home/mini-step-fpga/prj/h_brige/top.v(11[8:10])
    FD1P3IX tcr__i0 (.D(cmd_data[0]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[0]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i0.GSR = "DISABLED";
    LUT4 i2263_2_lut (.A(cmd_data[4]), .B(n15), .Z(n1008)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2263_2_lut.init = 16'hbbbb;
    LUT4 i2264_2_lut (.A(cmd_data[5]), .B(n15), .Z(n1007)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2264_2_lut.init = 16'hbbbb;
    LUT4 i2265_2_lut (.A(cmd_data[6]), .B(n15), .Z(n1006)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2265_2_lut.init = 16'h8888;
    LUT4 i386_3_lut_4_lut (.A(cmd[0]), .B(n4619), .C(rst_n), .D(cmd[1]), 
         .Z(clk_c_enable_45)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (C))) */ ;
    defparam i386_3_lut_4_lut.init = 16'h0f8f;
    FD1P3IX led_status__i2 (.D(cmd_data[2]), .SP(clk_c_enable_45), .CD(n4632), 
            .CK(clk_c), .Q(led_status[2]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam led_status__i2.GSR = "DISABLED";
    GSR GSR_INST (.GSR(rst_n));
    IB clk_pad (.I(clk), .O(clk_c));   // f:/home/mini-step-fpga/prj/h_brige/top.v(3[8:11])
    FD1P3IX led_status__i1 (.D(cmd_data[1]), .SP(clk_c_enable_45), .CD(n4632), 
            .CK(clk_c), .Q(led_status[1]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam led_status__i1.GSR = "DISABLED";
    FD1P3IX hcr__i0 (.D(cmd_data[0]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[0]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i0.GSR = "DISABLED";
    OB tx_pad (.I(tx_c), .O(tx));   // f:/home/mini-step-fpga/prj/h_brige/top.v(10[9:11])
    OB pwmb_pad (.I(pwmb_c), .O(pwmb));   // f:/home/mini-step-fpga/prj/h_brige/top.v(8[9:13])
    OB pwma_pad (.I(pwma_c), .O(pwma));   // f:/home/mini-step-fpga/prj/h_brige/top.v(7[9:13])
    LUT4 i2266_2_lut (.A(cmd_data[7]), .B(n15), .Z(n1005)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2266_2_lut.init = 16'h8888;
    LUT4 i2267_2_lut (.A(cmd_data[8]), .B(n15), .Z(n1004)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2267_2_lut.init = 16'h8888;
    LUT4 i2268_2_lut (.A(cmd_data[9]), .B(n15), .Z(n1003)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2268_2_lut.init = 16'h8888;
    LUT4 i2269_2_lut (.A(cmd_data[10]), .B(n15), .Z(n1002)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2269_2_lut.init = 16'h8888;
    TSALL TSALL_INST (.TSALL(GND_net));
    LUT4 i2270_2_lut (.A(cmd_data[11]), .B(n15), .Z(n1001)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2270_2_lut.init = 16'h8888;
    LUT4 equal_7_i10_2_lut_rep_61 (.A(cmd[2]), .B(cmd[3]), .Z(n4631)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(69[5:9])
    defparam equal_7_i10_2_lut_rep_61.init = 16'heeee;
    LUT4 i2271_2_lut (.A(cmd_data[12]), .B(n15), .Z(n1000)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2271_2_lut.init = 16'hbbbb;
    LUT4 i1_2_lut_rep_49_3_lut_4_lut (.A(cmd[2]), .B(cmd[3]), .C(n14), 
         .D(valid_o), .Z(n4619)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(69[5:9])
    defparam i1_2_lut_rep_49_3_lut_4_lut.init = 16'h0100;
    LUT4 i2272_2_lut (.A(cmd_data[13]), .B(n15), .Z(n999)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2272_2_lut.init = 16'hbbbb;
    LUT4 i2273_2_lut (.A(cmd_data[14]), .B(n15), .Z(n998)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2273_2_lut.init = 16'h8888;
    LUT4 i2274_2_lut (.A(cmd_data[15]), .B(n15), .Z(n997)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2274_2_lut.init = 16'h8888;
    LUT4 i2275_2_lut (.A(cmd_data[16]), .B(n15), .Z(n996)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2275_2_lut.init = 16'h8888;
    LUT4 i2276_2_lut (.A(cmd_data[17]), .B(n15), .Z(n995)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2276_2_lut.init = 16'h8888;
    LUT4 i2277_2_lut (.A(cmd_data[18]), .B(n15), .Z(n994)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2277_2_lut.init = 16'h8888;
    LUT4 i2278_2_lut (.A(cmd_data[19]), .B(n15), .Z(n993)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2278_2_lut.init = 16'h8888;
    FD1S3IX wr_33 (.D(valid_o), .CK(clk_c), .CD(n4632), .Q(wr));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_33.GSR = "DISABLED";
    FD1P3IX wr_data__i0 (.D(n1012), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[0]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i0.GSR = "DISABLED";
    LUT4 i2279_2_lut (.A(cmd_data[20]), .B(n15), .Z(n992)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2279_2_lut.init = 16'hbbbb;
    FD1P3IX cr_i6 (.D(cmd_data[6]), .SP(clk_c_enable_103), .CD(n4632), 
            .CK(clk_c), .Q(cr[6]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam cr_i6.GSR = "DISABLED";
    OB led_pad (.I(led_c), .O(led));   // f:/home/mini-step-fpga/prj/h_brige/top.v(5[9:12])
    LUT4 i2280_2_lut (.A(cmd_data[21]), .B(n15), .Z(n991)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2280_2_lut.init = 16'hbbbb;
    LUT4 i2281_2_lut (.A(cmd_data[22]), .B(n15), .Z(n990)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2281_2_lut.init = 16'h8888;
    LUT4 i2282_2_lut (.A(cmd_data[23]), .B(n15), .Z(n989)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2282_2_lut.init = 16'h8888;
    FD1P3IX cr_i5 (.D(cmd_data[5]), .SP(clk_c_enable_103), .CD(n4632), 
            .CK(clk_c), .Q(cr[5]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam cr_i5.GSR = "DISABLED";
    FD1P3IX cr_i4 (.D(cmd_data[4]), .SP(clk_c_enable_103), .CD(n4632), 
            .CK(clk_c), .Q(cr[4]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam cr_i4.GSR = "DISABLED";
    FD1P3IX cr_i3 (.D(cmd_data[3]), .SP(clk_c_enable_103), .CD(n4632), 
            .CK(clk_c), .Q(cr[3]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam cr_i3.GSR = "DISABLED";
    FD1P3IX cr_i2 (.D(cmd_data[2]), .SP(clk_c_enable_103), .CD(n4632), 
            .CK(clk_c), .Q(cr[2]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam cr_i2.GSR = "DISABLED";
    FD1P3IX cr_i1 (.D(cmd_data[1]), .SP(clk_c_enable_103), .CD(n4632), 
            .CK(clk_c), .Q(cr[1]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam cr_i1.GSR = "DISABLED";
    FD1P3IX tcr__i1 (.D(cmd_data[1]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[1]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i1.GSR = "DISABLED";
    FD1P3IX tcr__i2 (.D(cmd_data[2]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[2]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i2.GSR = "DISABLED";
    FD1P3IX tcr__i3 (.D(cmd_data[3]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[3]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i3.GSR = "DISABLED";
    FD1P3IX tcr__i4 (.D(cmd_data[4]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[4]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i4.GSR = "DISABLED";
    FD1P3IX tcr__i5 (.D(cmd_data[5]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[5]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i5.GSR = "DISABLED";
    FD1P3IX tcr__i6 (.D(cmd_data[6]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[6]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i6.GSR = "DISABLED";
    FD1P3IX tcr__i7 (.D(cmd_data[7]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[7]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i7.GSR = "DISABLED";
    FD1P3IX tcr__i8 (.D(cmd_data[8]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[8]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i8.GSR = "DISABLED";
    FD1P3IX tcr__i9 (.D(cmd_data[9]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[9]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i9.GSR = "DISABLED";
    FD1P3IX tcr__i10 (.D(cmd_data[10]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[10]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i10.GSR = "DISABLED";
    FD1P3IX tcr__i11 (.D(cmd_data[11]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[11]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i11.GSR = "DISABLED";
    FD1P3IX tcr__i12 (.D(cmd_data[12]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[12]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i12.GSR = "DISABLED";
    FD1P3IX tcr__i13 (.D(cmd_data[13]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[13]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i13.GSR = "DISABLED";
    FD1P3IX tcr__i14 (.D(cmd_data[14]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[14]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i14.GSR = "DISABLED";
    FD1P3IX tcr__i15 (.D(cmd_data[15]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[15]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i15.GSR = "DISABLED";
    FD1P3IX tcr__i16 (.D(cmd_data[16]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[16]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i16.GSR = "DISABLED";
    FD1P3IX tcr__i17 (.D(cmd_data[17]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[17]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i17.GSR = "DISABLED";
    FD1P3IX tcr__i18 (.D(cmd_data[18]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[18]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i18.GSR = "DISABLED";
    FD1P3IX tcr__i19 (.D(cmd_data[19]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[19]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i19.GSR = "DISABLED";
    FD1P3IX tcr__i20 (.D(cmd_data[20]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[20]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i20.GSR = "DISABLED";
    FD1P3IX tcr__i21 (.D(cmd_data[21]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[21]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i21.GSR = "DISABLED";
    FD1P3IX tcr__i22 (.D(cmd_data[22]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[22]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i22.GSR = "DISABLED";
    FD1P3IX tcr__i23 (.D(cmd_data[23]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[23]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i23.GSR = "DISABLED";
    FD1P3IX tcr__i24 (.D(cmd_data[24]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[24]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i24.GSR = "DISABLED";
    FD1P3IX tcr__i25 (.D(cmd_data[25]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[25]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i25.GSR = "DISABLED";
    FD1P3IX tcr__i26 (.D(cmd_data[26]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[26]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i26.GSR = "DISABLED";
    FD1P3IX tcr__i27 (.D(cmd_data[27]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[27]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i27.GSR = "DISABLED";
    FD1P3IX tcr__i28 (.D(cmd_data[28]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[28]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i28.GSR = "DISABLED";
    FD1P3IX tcr__i29 (.D(cmd_data[29]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[29]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i29.GSR = "DISABLED";
    FD1P3IX tcr__i30 (.D(cmd_data[30]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[30]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i30.GSR = "DISABLED";
    FD1P3IX tcr__i31 (.D(cmd_data[31]), .SP(clk_c_enable_147), .CD(n4632), 
            .CK(clk_c), .Q(tcr[31]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam tcr__i31.GSR = "DISABLED";
    LUT4 i2283_2_lut (.A(cmd_data[24]), .B(n15), .Z(n988)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2283_2_lut.init = 16'h8888;
    FD1P3JX cr_i0 (.D(cmd_data[0]), .SP(clk_c_enable_225), .PD(n4632), 
            .CK(clk_c), .Q(cr[0]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam cr_i0.GSR = "DISABLED";
    LUT4 i2284_2_lut (.A(cmd_data[25]), .B(n15), .Z(n987)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2284_2_lut.init = 16'h8888;
    FD1P3IX hcr__i1 (.D(cmd_data[1]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[1]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i1.GSR = "DISABLED";
    FD1P3IX hcr__i2 (.D(cmd_data[2]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[2]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i2.GSR = "DISABLED";
    FD1P3IX hcr__i3 (.D(cmd_data[3]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[3]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i3.GSR = "DISABLED";
    FD1P3IX hcr__i4 (.D(cmd_data[4]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[4]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i4.GSR = "DISABLED";
    FD1P3IX hcr__i5 (.D(cmd_data[5]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[5]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i5.GSR = "DISABLED";
    FD1P3IX hcr__i6 (.D(cmd_data[6]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[6]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i6.GSR = "DISABLED";
    FD1P3IX hcr__i7 (.D(cmd_data[7]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[7]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i7.GSR = "DISABLED";
    FD1P3IX hcr__i8 (.D(cmd_data[8]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[8]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i8.GSR = "DISABLED";
    FD1P3IX hcr__i9 (.D(cmd_data[9]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[9]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i9.GSR = "DISABLED";
    FD1P3IX hcr__i10 (.D(cmd_data[10]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[10]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i10.GSR = "DISABLED";
    FD1P3IX hcr__i11 (.D(cmd_data[11]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[11]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i11.GSR = "DISABLED";
    FD1P3IX hcr__i12 (.D(cmd_data[12]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[12]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i12.GSR = "DISABLED";
    FD1P3IX hcr__i13 (.D(cmd_data[13]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[13]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i13.GSR = "DISABLED";
    FD1P3IX hcr__i14 (.D(cmd_data[14]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[14]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i14.GSR = "DISABLED";
    FD1P3IX hcr__i15 (.D(cmd_data[15]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[15]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i15.GSR = "DISABLED";
    FD1P3IX hcr__i16 (.D(cmd_data[16]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[16]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i16.GSR = "DISABLED";
    FD1P3IX hcr__i17 (.D(cmd_data[17]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[17]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i17.GSR = "DISABLED";
    FD1P3IX hcr__i18 (.D(cmd_data[18]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[18]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i18.GSR = "DISABLED";
    FD1P3IX hcr__i19 (.D(cmd_data[19]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[19]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i19.GSR = "DISABLED";
    FD1P3IX hcr__i20 (.D(cmd_data[20]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[20]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i20.GSR = "DISABLED";
    FD1P3IX hcr__i21 (.D(cmd_data[21]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[21]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i21.GSR = "DISABLED";
    FD1P3IX hcr__i22 (.D(cmd_data[22]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[22]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i22.GSR = "DISABLED";
    FD1P3IX hcr__i23 (.D(cmd_data[23]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[23]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i23.GSR = "DISABLED";
    FD1P3IX hcr__i24 (.D(cmd_data[24]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[24]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i24.GSR = "DISABLED";
    FD1P3IX hcr__i25 (.D(cmd_data[25]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[25]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i25.GSR = "DISABLED";
    FD1P3IX hcr__i26 (.D(cmd_data[26]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[26]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i26.GSR = "DISABLED";
    FD1P3IX hcr__i27 (.D(cmd_data[27]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[27]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i27.GSR = "DISABLED";
    FD1P3IX hcr__i28 (.D(cmd_data[28]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[28]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i28.GSR = "DISABLED";
    FD1P3IX hcr__i29 (.D(cmd_data[29]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[29]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i29.GSR = "DISABLED";
    FD1P3IX hcr__i30 (.D(cmd_data[30]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[30]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i30.GSR = "DISABLED";
    FD1P3IX hcr__i31 (.D(cmd_data[31]), .SP(clk_c_enable_265), .CD(n4632), 
            .CK(clk_c), .Q(hcr[31]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam hcr__i31.GSR = "DISABLED";
    LUT4 i2285_2_lut (.A(cmd_data[26]), .B(n15), .Z(n986)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2285_2_lut.init = 16'h8888;
    LUT4 i2286_2_lut (.A(cmd_data[27]), .B(n15), .Z(n985)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2286_2_lut.init = 16'h8888;
    LUT4 i2287_2_lut (.A(cmd_data[28]), .B(n15), .Z(n984)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2287_2_lut.init = 16'hbbbb;
    LUT4 i2288_2_lut (.A(cmd_data[29]), .B(n15), .Z(n983)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2288_2_lut.init = 16'hbbbb;
    LUT4 i3_4_lut_adj_79 (.A(cmd[4]), .B(cmd[6]), .C(cmd[5]), .D(cmd[7]), 
         .Z(n14)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(70[5:9])
    defparam i3_4_lut_adj_79.init = 16'hfffe;
    LUT4 i2289_2_lut (.A(cmd_data[30]), .B(n15), .Z(n982)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2289_2_lut.init = 16'h8888;
    LUT4 i2290_2_lut (.A(cmd_data[31]), .B(n15), .Z(n981)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(65[4] 73[11])
    defparam i2290_2_lut.init = 16'h8888;
    LUT4 i1_3_lut_rep_43_4_lut (.A(n4627), .B(n4631), .C(cmd[1]), .D(cmd[0]), 
         .Z(clk_c_enable_103)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;
    defparam i1_3_lut_rep_43_4_lut.init = 16'h0020;
    FD1P3IX wr_data__i1 (.D(n1011), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[1]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i1.GSR = "DISABLED";
    FD1P3IX wr_data__i2 (.D(n1010), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[2]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i2.GSR = "DISABLED";
    FD1P3IX wr_data__i3 (.D(n1009), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[3]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i3.GSR = "DISABLED";
    FD1P3IX wr_data__i4 (.D(n1008), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[4]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i4.GSR = "DISABLED";
    FD1P3IX wr_data__i5 (.D(n1007), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[5]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i5.GSR = "DISABLED";
    FD1P3IX wr_data__i6 (.D(n1006), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[6]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i6.GSR = "DISABLED";
    FD1P3IX wr_data__i7 (.D(n1005), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[7]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i7.GSR = "DISABLED";
    FD1P3IX wr_data__i8 (.D(n1004), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[8]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i8.GSR = "DISABLED";
    FD1P3IX wr_data__i9 (.D(n1003), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[9]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i9.GSR = "DISABLED";
    FD1P3IX wr_data__i10 (.D(n1002), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[10]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i10.GSR = "DISABLED";
    FD1P3IX wr_data__i11 (.D(n1001), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[11]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i11.GSR = "DISABLED";
    FD1P3IX wr_data__i12 (.D(n1000), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[12]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i12.GSR = "DISABLED";
    FD1P3IX wr_data__i13 (.D(n999), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[13]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i13.GSR = "DISABLED";
    FD1P3IX wr_data__i14 (.D(n998), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[14]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i14.GSR = "DISABLED";
    FD1P3IX wr_data__i15 (.D(n997), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[15]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i15.GSR = "DISABLED";
    FD1P3IX wr_data__i16 (.D(n996), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[16]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i16.GSR = "DISABLED";
    FD1P3IX wr_data__i17 (.D(n995), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[17]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i17.GSR = "DISABLED";
    FD1P3IX wr_data__i18 (.D(n994), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[18]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i18.GSR = "DISABLED";
    FD1P3IX wr_data__i19 (.D(n993), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[19]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i19.GSR = "DISABLED";
    FD1P3IX wr_data__i20 (.D(n992), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[20]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i20.GSR = "DISABLED";
    FD1P3IX wr_data__i21 (.D(n991), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[21]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i21.GSR = "DISABLED";
    FD1P3IX wr_data__i22 (.D(n990), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[22]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i22.GSR = "DISABLED";
    FD1P3IX wr_data__i23 (.D(n989), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[23]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i23.GSR = "DISABLED";
    FD1P3IX wr_data__i24 (.D(n988), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[24]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i24.GSR = "DISABLED";
    FD1P3IX wr_data__i25 (.D(n987), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[25]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i25.GSR = "DISABLED";
    FD1P3IX wr_data__i26 (.D(n986), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[26]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i26.GSR = "DISABLED";
    FD1P3IX wr_data__i27 (.D(n985), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[27]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i27.GSR = "DISABLED";
    FD1P3IX wr_data__i28 (.D(n984), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[28]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i28.GSR = "DISABLED";
    FD1P3IX wr_data__i29 (.D(n983), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[29]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i29.GSR = "DISABLED";
    FD1P3IX wr_data__i30 (.D(n982), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[30]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i30.GSR = "DISABLED";
    FD1P3IX wr_data__i31 (.D(n981), .SP(clk_c_enable_296), .CD(n4632), 
            .CK(clk_c), .Q(wr_data[31]));   // f:/home/mini-step-fpga/prj/h_brige/top.v(52[8] 77[4])
    defparam wr_data__i31.GSR = "DISABLED";
    LUT4 i3156_3_lut (.A(cmd[0]), .B(cmd[3]), .C(cmd[1]), .Z(n4332)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i3156_3_lut.init = 16'hfefe;
    VLO i1 (.Z(GND_net));
    full_brige_driver u_full_brige_driver (.tcr({tcr}), .\cr[6] (cr[6]), 
            .pwma_c(pwma_c), .clk_c(clk_c), .pwmb_c(pwmb_c), .clk_c_enable_216(clk_c_enable_216), 
            .n4632(n4632), .hcr({hcr}), .\cr[1] (cr[1]), .\cr[4] (cr[4]), 
            .\cr[5] (cr[5]), .\cr[2] (cr[2]), .ope(ope), .\cr[3] (cr[3]), 
            .GND_net(GND_net), .\cr[0] (cr[0]), .rst_n(rst_n)) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(40[3] 50[2])
    LUT4 m1_lut (.Z(n4932)) /* synthesis lut_function=1, syn_instantiated=1 */ ;
    defparam m1_lut.init = 16'hffff;
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    Rst_sys Rst_sys_uu (.rst_n(rst_n), .clk_c(clk_c), .GND_net(GND_net)) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(15[10:32])
    Debug_core Debug_uut (.clk_c(clk_c), .wr_data({wr_data}), .rst_n(rst_n), 
            .wr(wr), .tx_c(tx_c), .GND_net(GND_net), .rx_c(rx_c), .valid_o(valid_o), 
            .n4932(n4932), .cmd({cmd}), .cmd_data({cmd_data}), .n4632(n4632), 
            .n4619(n4619), .clk_c_enable_225(clk_c_enable_225), .clk_c_enable_147(clk_c_enable_147), 
            .clk_c_enable_296(clk_c_enable_296), .n4627(n4627), .n4332(n4332), 
            .clk_c_enable_265(clk_c_enable_265), .ope(ope), .clk_c_enable_216(clk_c_enable_216)) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(83[3] 94[2])
    LedStatus LedStatus (.led_c(led_c), .clk_c(clk_c), .led_status({led_status}), 
            .GND_net(GND_net)) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(28[3] 33[2])
    VHI i3339 (.Z(VCC_net));
    
endmodule
//
// Verilog Description of module TSALL
// module not written out since it is a black-box. 
//

//
// Verilog Description of module full_brige_driver
//

module full_brige_driver (tcr, \cr[6] , pwma_c, clk_c, pwmb_c, clk_c_enable_216, 
            n4632, hcr, \cr[1] , \cr[4] , \cr[5] , \cr[2] , ope, 
            \cr[3] , GND_net, \cr[0] , rst_n) /* synthesis syn_module_defined=1 */ ;
    input [31:0]tcr;
    input \cr[6] ;
    output pwma_c;
    input clk_c;
    output pwmb_c;
    input clk_c_enable_216;
    input n4632;
    input [31:0]hcr;
    input \cr[1] ;
    input \cr[4] ;
    input \cr[5] ;
    input \cr[2] ;
    output ope;
    input \cr[3] ;
    input GND_net;
    input \cr[0] ;
    input rst_n;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(3[8:11])
    
    wire pwma_N_633;
    wire [31:0]clkcnt;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(53[17:23])
    wire [31:0]n4;
    wire [31:0]clkcnt_31__N_559;
    
    wire ope_N_649, pwma_N_626, pwmb_N_640;
    wire [31:0]hcr_r;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(57[12:17])
    
    wire pwma_N_628, n2559, n4305, n2176, pwma_N_632, n55, n60, 
        n49, n50, n48, n39, n58, n52, n40, clkcnt_31__N_591, 
        n1, pwmb_N_642, n4351, n54, n44, pwmb_N_643, pwma_N_639, 
        pwma_N_637, n55_adj_1047, n60_adj_1048, n49_adj_1049, n50_adj_1050, 
        dir_f, n48_adj_1051, n39_adj_1052, n58_adj_1053, n52_adj_1054, 
        n40_adj_1055, n4607, n54_adj_1056, n44_adj_1057, n3857, n3856, 
        n3855, n3854, n3853, n3852, n3851, n3850, n3849, pwmb_N_645, 
        n3848, n3847, n3846, n3845, n3844, n3843, n3842, n3825, 
        n3824, n3823, n3822, n3821, n3820, n3819, n3818, n3817, 
        n3816, n3815, n3814, n3813, n3812, n3811, n3810;
    
    LUT4 mux_6_i2_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[1]), 
         .D(tcr[1]), .Z(clkcnt_31__N_559[1])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i2_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i3220_2_lut_3_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(\cr[6] ), 
         .Z(ope_N_649)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam i3220_2_lut_3_lut.init = 16'h1f1f;
    LUT4 mux_6_i12_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[11]), 
         .D(tcr[11]), .Z(clkcnt_31__N_559[11])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i12_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_6_i1_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[0]), 
         .D(tcr[0]), .Z(clkcnt_31__N_559[0])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i1_3_lut_4_lut.init = 16'hf1e0;
    FD1S3AX pwma_57 (.D(pwma_N_626), .CK(clk_c), .Q(pwma_c)) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(91[8] 124[4])
    defparam pwma_57.GSR = "DISABLED";
    LUT4 mux_6_i23_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[22]), 
         .D(tcr[22]), .Z(clkcnt_31__N_559[22])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i23_3_lut_4_lut.init = 16'hf1e0;
    FD1S3AX pwmb_58 (.D(pwmb_N_640), .CK(clk_c), .Q(pwmb_c)) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(91[8] 124[4])
    defparam pwmb_58.GSR = "DISABLED";
    LUT4 mux_6_i22_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[21]), 
         .D(tcr[21]), .Z(clkcnt_31__N_559[21])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i22_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_6_i21_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[20]), 
         .D(tcr[20]), .Z(clkcnt_31__N_559[20])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i21_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_6_i11_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[10]), 
         .D(tcr[10]), .Z(clkcnt_31__N_559[10])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i11_3_lut_4_lut.init = 16'hf1e0;
    FD1P3IX hcr_r__i0 (.D(hcr[0]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[0])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i0.GSR = "DISABLED";
    LUT4 i724_4_lut (.A(pwma_N_628), .B(\cr[1] ), .C(n2559), .D(n4305), 
         .Z(pwma_N_626)) /* synthesis lut_function=(A (B+!(C+(D)))+!A (B (C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(120[14] 123[8])
    defparam i724_4_lut.init = 16'hccca;
    LUT4 cr_5__I_0_66_i3_4_lut (.A(n2176), .B(\cr[4] ), .C(\cr[5] ), .D(hcr_r[31]), 
         .Z(pwma_N_628)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(97[13] 118[20])
    defparam cr_5__I_0_66_i3_4_lut.init = 16'hc0ca;
    LUT4 i1066_4_lut (.A(\cr[1] ), .B(\cr[4] ), .C(pwma_N_632), .D(pwma_N_633), 
         .Z(n2176)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A !(B (C (D))+!B (C)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(97[13] 118[20])
    defparam i1066_4_lut.init = 16'h5a9a;
    LUT4 i30_4_lut (.A(n55), .B(n60), .C(n49), .D(n50), .Z(pwma_N_633)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam i30_4_lut.init = 16'hfffe;
    LUT4 mux_6_i20_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[19]), 
         .D(tcr[19]), .Z(clkcnt_31__N_559[19])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i20_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i24_4_lut (.A(clkcnt[23]), .B(n48), .C(clkcnt[15]), .D(clkcnt[5]), 
         .Z(n55)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam i24_4_lut.init = 16'hfffe;
    LUT4 i29_4_lut (.A(n39), .B(n58), .C(n52), .D(n40), .Z(n60)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam i29_4_lut.init = 16'hfffe;
    LUT4 i18_4_lut (.A(clkcnt[25]), .B(clkcnt[3]), .C(clkcnt[28]), .D(clkcnt[12]), 
         .Z(n49)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam i18_4_lut.init = 16'hfffe;
    LUT4 i19_4_lut (.A(clkcnt[18]), .B(clkcnt[2]), .C(clkcnt[20]), .D(clkcnt[4]), 
         .Z(n50)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam i19_4_lut.init = 16'hfffe;
    FD1S3IX clkcnt__i31 (.D(clkcnt_31__N_559[31]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[31])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i31.GSR = "DISABLED";
    FD1S3IX clkcnt__i30 (.D(clkcnt_31__N_559[30]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[30])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i30.GSR = "DISABLED";
    FD1S3IX clkcnt__i29 (.D(clkcnt_31__N_559[29]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[29])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i29.GSR = "DISABLED";
    FD1S3IX clkcnt__i28 (.D(clkcnt_31__N_559[28]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[28])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i28.GSR = "DISABLED";
    FD1S3IX clkcnt__i27 (.D(clkcnt_31__N_559[27]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[27])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i27.GSR = "DISABLED";
    FD1S3IX clkcnt__i26 (.D(clkcnt_31__N_559[26]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[26])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i26.GSR = "DISABLED";
    LUT4 mux_6_i19_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[18]), 
         .D(tcr[18]), .Z(clkcnt_31__N_559[18])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i19_3_lut_4_lut.init = 16'hf1e0;
    FD1S3IX clkcnt__i25 (.D(clkcnt_31__N_559[25]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[25])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i25.GSR = "DISABLED";
    FD1S3IX clkcnt__i24 (.D(clkcnt_31__N_559[24]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[24])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i24.GSR = "DISABLED";
    PFUMX i726 (.BLUT(n1), .ALUT(pwmb_N_642), .C0(n4351), .Z(pwmb_N_640));
    FD1S3IX clkcnt__i23 (.D(clkcnt_31__N_559[23]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[23])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i23.GSR = "DISABLED";
    FD1S3IX clkcnt__i22 (.D(clkcnt_31__N_559[22]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[22])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i22.GSR = "DISABLED";
    LUT4 mux_6_i18_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[17]), 
         .D(tcr[17]), .Z(clkcnt_31__N_559[17])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i18_3_lut_4_lut.init = 16'hf1e0;
    FD1S3IX clkcnt__i21 (.D(clkcnt_31__N_559[21]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[21])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i21.GSR = "DISABLED";
    LUT4 mux_6_i17_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[16]), 
         .D(tcr[16]), .Z(clkcnt_31__N_559[16])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i17_3_lut_4_lut.init = 16'hf1e0;
    FD1S3IX clkcnt__i20 (.D(clkcnt_31__N_559[20]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[20])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i20.GSR = "DISABLED";
    FD1S3IX clkcnt__i19 (.D(clkcnt_31__N_559[19]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[19])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i19.GSR = "DISABLED";
    FD1S3IX clkcnt__i18 (.D(clkcnt_31__N_559[18]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[18])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i18.GSR = "DISABLED";
    FD1S3IX clkcnt__i17 (.D(clkcnt_31__N_559[17]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[17])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i17.GSR = "DISABLED";
    FD1S3IX clkcnt__i16 (.D(clkcnt_31__N_559[16]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[16])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i16.GSR = "DISABLED";
    FD1S3IX clkcnt__i15 (.D(clkcnt_31__N_559[15]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[15])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i15.GSR = "DISABLED";
    LUT4 i17_4_lut (.A(clkcnt[24]), .B(clkcnt[0]), .C(clkcnt[8]), .D(clkcnt[14]), 
         .Z(n48)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam i17_4_lut.init = 16'hfffe;
    LUT4 mux_6_i28_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[27]), 
         .D(tcr[27]), .Z(clkcnt_31__N_559[27])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i28_3_lut_4_lut.init = 16'hf1e0;
    FD1S3IX clkcnt__i14 (.D(clkcnt_31__N_559[14]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[14])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i14.GSR = "DISABLED";
    FD1S3IX clkcnt__i13 (.D(clkcnt_31__N_559[13]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[13])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i13.GSR = "DISABLED";
    FD1S3IX clkcnt__i12 (.D(clkcnt_31__N_559[12]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[12])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i12.GSR = "DISABLED";
    LUT4 i8_2_lut (.A(clkcnt[16]), .B(clkcnt[30]), .Z(n39)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam i8_2_lut.init = 16'heeee;
    FD1S3IX clkcnt__i11 (.D(clkcnt_31__N_559[11]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[11])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i11.GSR = "DISABLED";
    FD1S3IX clkcnt__i10 (.D(clkcnt_31__N_559[10]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[10])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i10.GSR = "DISABLED";
    FD1S3IX clkcnt__i9 (.D(clkcnt_31__N_559[9]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[9])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i9.GSR = "DISABLED";
    FD1S3IX clkcnt__i8 (.D(clkcnt_31__N_559[8]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[8])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i8.GSR = "DISABLED";
    FD1S3IX clkcnt__i7 (.D(clkcnt_31__N_559[7]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[7])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i7.GSR = "DISABLED";
    FD1S3IX clkcnt__i6 (.D(clkcnt_31__N_559[6]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[6])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i6.GSR = "DISABLED";
    FD1S3IX clkcnt__i5 (.D(clkcnt_31__N_559[5]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[5])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i5.GSR = "DISABLED";
    FD1S3IX clkcnt__i4 (.D(clkcnt_31__N_559[4]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[4])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i4.GSR = "DISABLED";
    FD1S3IX clkcnt__i3 (.D(clkcnt_31__N_559[3]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[3])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i3.GSR = "DISABLED";
    FD1S3IX clkcnt__i2 (.D(clkcnt_31__N_559[2]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[2])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i2.GSR = "DISABLED";
    LUT4 i27_4_lut (.A(clkcnt[10]), .B(n54), .C(n44), .D(clkcnt[17]), 
         .Z(n58)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam i27_4_lut.init = 16'hfffe;
    FD1S3IX clkcnt__i1 (.D(clkcnt_31__N_559[1]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[1])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i1.GSR = "DISABLED";
    LUT4 i21_4_lut (.A(clkcnt[21]), .B(clkcnt[26]), .C(clkcnt[22]), .D(clkcnt[9]), 
         .Z(n52)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam i21_4_lut.init = 16'hfffe;
    LUT4 i9_2_lut (.A(clkcnt[11]), .B(clkcnt[13]), .Z(n40)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam i9_2_lut.init = 16'heeee;
    LUT4 i23_4_lut (.A(clkcnt[29]), .B(clkcnt[19]), .C(clkcnt[7]), .D(clkcnt[6]), 
         .Z(n54)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam i23_4_lut.init = 16'hfffe;
    LUT4 i3223_2_lut_4_lut (.A(\cr[4] ), .B(n4305), .C(\cr[5] ), .D(hcr_r[31]), 
         .Z(n4351)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B+(C+!(D)))) */ ;
    defparam i3223_2_lut_4_lut.init = 16'hfefd;
    LUT4 mux_6_i16_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[15]), 
         .D(tcr[15]), .Z(clkcnt_31__N_559[15])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i16_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_6_i27_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[26]), 
         .D(tcr[26]), .Z(clkcnt_31__N_559[26])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i27_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i13_2_lut (.A(clkcnt[1]), .B(clkcnt[27]), .Z(n44)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam i13_2_lut.init = 16'heeee;
    LUT4 mux_6_i26_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[25]), 
         .D(tcr[25]), .Z(clkcnt_31__N_559[25])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i26_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_6_i15_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[14]), 
         .D(tcr[14]), .Z(clkcnt_31__N_559[14])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i15_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i1447_2_lut (.A(hcr_r[31]), .B(\cr[5] ), .Z(n2559)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(120[14] 123[8])
    defparam i1447_2_lut.init = 16'h2222;
    LUT4 mux_6_i14_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[13]), 
         .D(tcr[13]), .Z(clkcnt_31__N_559[13])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i14_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i2167_4_lut_4_lut (.A(hcr_r[31]), .B(pwma_N_633), .C(pwma_N_632), 
         .D(\cr[2] ), .Z(pwmb_N_643)) /* synthesis lut_function=(!(A+(B (C (D)+!C !(D))+!B !(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam i2167_4_lut_4_lut.init = 16'h1540;
    LUT4 mux_6_i13_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[12]), 
         .D(tcr[12]), .Z(clkcnt_31__N_559[12])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i13_3_lut_4_lut.init = 16'hf1e0;
    FD1S3IX ope_56 (.D(ope_N_649), .CK(clk_c), .CD(n4632), .Q(ope));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam ope_56.GSR = "DISABLED";
    LUT4 i1_4_lut (.A(clkcnt_31__N_591), .B(\cr[3] ), .C(pwma_N_639), 
         .D(pwma_N_637), .Z(n4305)) /* synthesis lut_function=(A+(B ((D)+!C)+!B !(C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(120[14] 123[8])
    defparam i1_4_lut.init = 16'hefaf;
    LUT4 i30_4_lut_adj_67 (.A(n55_adj_1047), .B(n60_adj_1048), .C(n49_adj_1049), 
         .D(n50_adj_1050), .Z(pwma_N_639)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(92[21:35])
    defparam i30_4_lut_adj_67.init = 16'hfffe;
    LUT4 dir_f_I_0_2_lut (.A(dir_f), .B(hcr_r[31]), .Z(pwma_N_637)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(93[22:43])
    defparam dir_f_I_0_2_lut.init = 16'h6666;
    FD1S3IX dir_f_55 (.D(hcr_r[31]), .CK(clk_c), .CD(n4632), .Q(dir_f));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam dir_f_55.GSR = "DISABLED";
    LUT4 i24_4_lut_adj_68 (.A(hcr_r[14]), .B(n48_adj_1051), .C(hcr_r[30]), 
         .D(hcr_r[2]), .Z(n55_adj_1047)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(92[21:35])
    defparam i24_4_lut_adj_68.init = 16'hfffe;
    LUT4 i29_4_lut_adj_69 (.A(n39_adj_1052), .B(n58_adj_1053), .C(n52_adj_1054), 
         .D(n40_adj_1055), .Z(n60_adj_1048)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(92[21:35])
    defparam i29_4_lut_adj_69.init = 16'hfffe;
    LUT4 i18_4_lut_adj_70 (.A(hcr_r[21]), .B(hcr_r[27]), .C(hcr_r[25]), 
         .D(hcr_r[9]), .Z(n49_adj_1049)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(92[21:35])
    defparam i18_4_lut_adj_70.init = 16'hfffe;
    LUT4 i19_4_lut_adj_71 (.A(hcr_r[16]), .B(hcr_r[1]), .C(hcr_r[17]), 
         .D(hcr_r[3]), .Z(n50_adj_1050)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(92[21:35])
    defparam i19_4_lut_adj_71.init = 16'hfffe;
    LUT4 cr_4__bdd_4_lut_rep_37 (.A(\cr[4] ), .B(n4305), .C(\cr[5] ), 
         .D(hcr_r[31]), .Z(n4607)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B+!(C+(D)))) */ ;
    defparam cr_4__bdd_4_lut_rep_37.init = 16'hcecd;
    LUT4 i17_4_lut_adj_72 (.A(hcr_r[19]), .B(hcr_r[0]), .C(hcr_r[7]), 
         .D(hcr_r[12]), .Z(n48_adj_1051)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(92[21:35])
    defparam i17_4_lut_adj_72.init = 16'hfffe;
    LUT4 i8_2_lut_adj_73 (.A(hcr_r[15]), .B(hcr_r[28]), .Z(n39_adj_1052)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(92[21:35])
    defparam i8_2_lut_adj_73.init = 16'heeee;
    LUT4 i27_4_lut_adj_74 (.A(hcr_r[8]), .B(n54_adj_1056), .C(n44_adj_1057), 
         .D(hcr_r[11]), .Z(n58_adj_1053)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(92[21:35])
    defparam i27_4_lut_adj_74.init = 16'hfffe;
    LUT4 i21_4_lut_adj_75 (.A(hcr_r[18]), .B(hcr_r[24]), .C(hcr_r[20]), 
         .D(hcr_r[5]), .Z(n52_adj_1054)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(92[21:35])
    defparam i21_4_lut_adj_75.init = 16'hfffe;
    LUT4 i9_2_lut_adj_76 (.A(hcr_r[6]), .B(hcr_r[10]), .Z(n40_adj_1055)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(92[21:35])
    defparam i9_2_lut_adj_76.init = 16'heeee;
    LUT4 i23_4_lut_adj_77 (.A(hcr_r[26]), .B(hcr_r[13]), .C(hcr_r[29]), 
         .D(hcr_r[4]), .Z(n54_adj_1056)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(92[21:35])
    defparam i23_4_lut_adj_77.init = 16'hfffe;
    FD1P3IX hcr_r__i1 (.D(hcr[1]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[1])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i1.GSR = "DISABLED";
    LUT4 i13_2_lut_adj_78 (.A(hcr_r[23]), .B(hcr_r[22]), .Z(n44_adj_1057)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(92[21:35])
    defparam i13_2_lut_adj_78.init = 16'heeee;
    FD1P3IX hcr_r__i2 (.D(hcr[2]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[2])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i2.GSR = "DISABLED";
    FD1P3IX hcr_r__i3 (.D(hcr[3]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[3])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i3.GSR = "DISABLED";
    FD1P3IX hcr_r__i4 (.D(hcr[4]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[4])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i4.GSR = "DISABLED";
    FD1P3IX hcr_r__i5 (.D(hcr[5]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[5])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i5.GSR = "DISABLED";
    FD1P3IX hcr_r__i6 (.D(hcr[6]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[6])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i6.GSR = "DISABLED";
    FD1P3IX hcr_r__i7 (.D(hcr[7]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[7])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i7.GSR = "DISABLED";
    FD1P3IX hcr_r__i8 (.D(hcr[8]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[8])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i8.GSR = "DISABLED";
    FD1P3IX hcr_r__i9 (.D(hcr[9]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[9])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i9.GSR = "DISABLED";
    FD1P3IX hcr_r__i10 (.D(hcr[10]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[10])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i10.GSR = "DISABLED";
    FD1P3IX hcr_r__i11 (.D(hcr[11]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[11])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i11.GSR = "DISABLED";
    FD1P3IX hcr_r__i12 (.D(hcr[12]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[12])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i12.GSR = "DISABLED";
    FD1P3IX hcr_r__i13 (.D(hcr[13]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[13])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i13.GSR = "DISABLED";
    FD1P3IX hcr_r__i14 (.D(hcr[14]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[14])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i14.GSR = "DISABLED";
    FD1P3IX hcr_r__i15 (.D(hcr[15]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[15])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i15.GSR = "DISABLED";
    FD1P3IX hcr_r__i16 (.D(hcr[16]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[16])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i16.GSR = "DISABLED";
    FD1P3IX hcr_r__i17 (.D(hcr[17]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[17])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i17.GSR = "DISABLED";
    FD1P3IX hcr_r__i18 (.D(hcr[18]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[18])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i18.GSR = "DISABLED";
    FD1P3IX hcr_r__i19 (.D(hcr[19]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[19])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i19.GSR = "DISABLED";
    FD1P3IX hcr_r__i20 (.D(hcr[20]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[20])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i20.GSR = "DISABLED";
    FD1P3IX hcr_r__i21 (.D(hcr[21]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[21])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i21.GSR = "DISABLED";
    FD1P3IX hcr_r__i22 (.D(hcr[22]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[22])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i22.GSR = "DISABLED";
    FD1P3IX hcr_r__i23 (.D(hcr[23]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[23])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i23.GSR = "DISABLED";
    FD1P3IX hcr_r__i24 (.D(hcr[24]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[24])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i24.GSR = "DISABLED";
    FD1P3IX hcr_r__i25 (.D(hcr[25]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[25])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i25.GSR = "DISABLED";
    FD1P3IX hcr_r__i26 (.D(hcr[26]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[26])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i26.GSR = "DISABLED";
    FD1P3IX hcr_r__i27 (.D(hcr[27]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[27])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i27.GSR = "DISABLED";
    FD1P3IX hcr_r__i28 (.D(hcr[28]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[28])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i28.GSR = "DISABLED";
    FD1P3IX hcr_r__i29 (.D(hcr[29]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[29])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i29.GSR = "DISABLED";
    FD1P3IX hcr_r__i30 (.D(hcr[30]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[30])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i30.GSR = "DISABLED";
    FD1P3IX hcr_r__i31 (.D(hcr[31]), .SP(clk_c_enable_216), .CD(n4632), 
            .CK(clk_c), .Q(hcr_r[31])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(77[8] 89[4])
    defparam hcr_r__i31.GSR = "DISABLED";
    FD1S3IX clkcnt__i0 (.D(clkcnt_31__N_559[0]), .CK(clk_c), .CD(clkcnt_31__N_591), 
            .Q(clkcnt[0])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=40, LSE_RLINE=50 */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(70[8] 75[4])
    defparam clkcnt__i0.GSR = "DISABLED";
    CCU2D sub_5_add_2_33 (.A0(clkcnt[31]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3857), .S0(n4[31]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_33.INIT0 = 16'h5555;
    defparam sub_5_add_2_33.INIT1 = 16'h0000;
    defparam sub_5_add_2_33.INJECT1_0 = "NO";
    defparam sub_5_add_2_33.INJECT1_1 = "NO";
    CCU2D sub_5_add_2_31 (.A0(clkcnt[29]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clkcnt[30]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3856), .COUT(n3857), .S0(n4[29]), .S1(n4[30]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_31.INIT0 = 16'h5555;
    defparam sub_5_add_2_31.INIT1 = 16'h5555;
    defparam sub_5_add_2_31.INJECT1_0 = "NO";
    defparam sub_5_add_2_31.INJECT1_1 = "NO";
    LUT4 mux_6_i6_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[5]), 
         .D(tcr[5]), .Z(clkcnt_31__N_559[5])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i6_3_lut_4_lut.init = 16'hf1e0;
    CCU2D sub_5_add_2_29 (.A0(clkcnt[27]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clkcnt[28]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3855), .COUT(n3856), .S0(n4[27]), .S1(n4[28]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_29.INIT0 = 16'h5555;
    defparam sub_5_add_2_29.INIT1 = 16'h5555;
    defparam sub_5_add_2_29.INJECT1_0 = "NO";
    defparam sub_5_add_2_29.INJECT1_1 = "NO";
    CCU2D sub_5_add_2_27 (.A0(clkcnt[25]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clkcnt[26]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3854), .COUT(n3855), .S0(n4[25]), .S1(n4[26]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_27.INIT0 = 16'h5555;
    defparam sub_5_add_2_27.INIT1 = 16'h5555;
    defparam sub_5_add_2_27.INJECT1_0 = "NO";
    defparam sub_5_add_2_27.INJECT1_1 = "NO";
    LUT4 i3195_2_lut (.A(\cr[0] ), .B(rst_n), .Z(clkcnt_31__N_591)) /* synthesis lut_function=(!(A (B))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(92[8:18])
    defparam i3195_2_lut.init = 16'h7777;
    CCU2D sub_5_add_2_25 (.A0(clkcnt[23]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clkcnt[24]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3853), .COUT(n3854), .S0(n4[23]), .S1(n4[24]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_25.INIT0 = 16'h5555;
    defparam sub_5_add_2_25.INIT1 = 16'h5555;
    defparam sub_5_add_2_25.INJECT1_0 = "NO";
    defparam sub_5_add_2_25.INJECT1_1 = "NO";
    CCU2D sub_5_add_2_23 (.A0(clkcnt[21]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clkcnt[22]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3852), .COUT(n3853), .S0(n4[21]), .S1(n4[22]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_23.INIT0 = 16'h5555;
    defparam sub_5_add_2_23.INIT1 = 16'h5555;
    defparam sub_5_add_2_23.INJECT1_0 = "NO";
    defparam sub_5_add_2_23.INJECT1_1 = "NO";
    LUT4 mux_6_i5_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[4]), 
         .D(tcr[4]), .Z(clkcnt_31__N_559[4])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i5_3_lut_4_lut.init = 16'hf1e0;
    CCU2D sub_5_add_2_21 (.A0(clkcnt[19]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clkcnt[20]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3851), .COUT(n3852), .S0(n4[19]), .S1(n4[20]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_21.INIT0 = 16'h5555;
    defparam sub_5_add_2_21.INIT1 = 16'h5555;
    defparam sub_5_add_2_21.INJECT1_0 = "NO";
    defparam sub_5_add_2_21.INJECT1_1 = "NO";
    CCU2D sub_5_add_2_19 (.A0(clkcnt[17]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clkcnt[18]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3850), .COUT(n3851), .S0(n4[17]), .S1(n4[18]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_19.INIT0 = 16'h5555;
    defparam sub_5_add_2_19.INIT1 = 16'h5555;
    defparam sub_5_add_2_19.INJECT1_0 = "NO";
    defparam sub_5_add_2_19.INJECT1_1 = "NO";
    CCU2D sub_5_add_2_17 (.A0(clkcnt[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clkcnt[16]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3849), .COUT(n3850), .S0(n4[15]), .S1(n4[16]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_17.INIT0 = 16'h5555;
    defparam sub_5_add_2_17.INIT1 = 16'h5555;
    defparam sub_5_add_2_17.INJECT1_0 = "NO";
    defparam sub_5_add_2_17.INJECT1_1 = "NO";
    LUT4 mux_6_i4_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[3]), 
         .D(tcr[3]), .Z(clkcnt_31__N_559[3])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i4_3_lut_4_lut.init = 16'hf1e0;
    LUT4 i2166_3_lut (.A(\cr[2] ), .B(hcr_r[31]), .C(pwma_N_632), .Z(pwmb_N_645)) /* synthesis lut_function=(!(A ((C)+!B)+!A !(B (C)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(101[33:116])
    defparam i2166_3_lut.init = 16'h4848;
    CCU2D sub_5_add_2_15 (.A0(clkcnt[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clkcnt[14]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3848), .COUT(n3849), .S0(n4[13]), .S1(n4[14]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_15.INIT0 = 16'h5555;
    defparam sub_5_add_2_15.INIT1 = 16'h5555;
    defparam sub_5_add_2_15.INJECT1_0 = "NO";
    defparam sub_5_add_2_15.INJECT1_1 = "NO";
    CCU2D sub_5_add_2_13 (.A0(clkcnt[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clkcnt[12]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3847), .COUT(n3848), .S0(n4[11]), .S1(n4[12]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_13.INIT0 = 16'h5555;
    defparam sub_5_add_2_13.INIT1 = 16'h5555;
    defparam sub_5_add_2_13.INJECT1_0 = "NO";
    defparam sub_5_add_2_13.INJECT1_1 = "NO";
    CCU2D sub_5_add_2_11 (.A0(clkcnt[9]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clkcnt[10]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3846), .COUT(n3847), .S0(n4[9]), .S1(n4[10]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_11.INIT0 = 16'h5555;
    defparam sub_5_add_2_11.INIT1 = 16'h5555;
    defparam sub_5_add_2_11.INJECT1_0 = "NO";
    defparam sub_5_add_2_11.INJECT1_1 = "NO";
    LUT4 cr_5__I_0_i3_3_lut (.A(\cr[4] ), .B(\cr[2] ), .C(n4607), .Z(pwmb_N_642)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(97[13] 118[20])
    defparam cr_5__I_0_i3_3_lut.init = 16'hcaca;
    CCU2D sub_5_add_2_9 (.A0(clkcnt[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(clkcnt[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3845), .COUT(n3846), .S0(n4[7]), .S1(n4[8]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_9.INIT0 = 16'h5555;
    defparam sub_5_add_2_9.INIT1 = 16'h5555;
    defparam sub_5_add_2_9.INJECT1_0 = "NO";
    defparam sub_5_add_2_9.INJECT1_1 = "NO";
    LUT4 mux_6_i32_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[31]), 
         .D(tcr[31]), .Z(clkcnt_31__N_559[31])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i32_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_6_i31_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[30]), 
         .D(tcr[30]), .Z(clkcnt_31__N_559[30])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i31_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_6_i10_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[9]), 
         .D(tcr[9]), .Z(clkcnt_31__N_559[9])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i10_3_lut_4_lut.init = 16'hf1e0;
    CCU2D sub_5_add_2_7 (.A0(clkcnt[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(clkcnt[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3844), .COUT(n3845), .S0(n4[5]), .S1(n4[6]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_7.INIT0 = 16'h5555;
    defparam sub_5_add_2_7.INIT1 = 16'h5555;
    defparam sub_5_add_2_7.INJECT1_0 = "NO";
    defparam sub_5_add_2_7.INJECT1_1 = "NO";
    CCU2D sub_5_add_2_5 (.A0(clkcnt[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(clkcnt[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3843), .COUT(n3844), .S0(n4[3]), .S1(n4[4]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_5.INIT0 = 16'h5555;
    defparam sub_5_add_2_5.INIT1 = 16'h5555;
    defparam sub_5_add_2_5.INJECT1_0 = "NO";
    defparam sub_5_add_2_5.INJECT1_1 = "NO";
    CCU2D sub_5_add_2_3 (.A0(clkcnt[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(clkcnt[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3842), .COUT(n3843), .S0(n4[1]), .S1(n4[2]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_3.INIT0 = 16'h5555;
    defparam sub_5_add_2_3.INIT1 = 16'h5555;
    defparam sub_5_add_2_3.INJECT1_0 = "NO";
    defparam sub_5_add_2_3.INJECT1_1 = "NO";
    CCU2D sub_5_add_2_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(clkcnt[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .COUT(n3842), .S1(n4[0]));   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(72[38:51])
    defparam sub_5_add_2_1.INIT0 = 16'hF000;
    defparam sub_5_add_2_1.INIT1 = 16'h5555;
    defparam sub_5_add_2_1.INJECT1_0 = "NO";
    defparam sub_5_add_2_1.INJECT1_1 = "NO";
    LUT4 i3190_3_lut (.A(pwmb_N_645), .B(pwmb_N_643), .C(\cr[4] ), .Z(n1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(120[14] 123[8])
    defparam i3190_3_lut.init = 16'hcaca;
    LUT4 mux_6_i9_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[8]), 
         .D(tcr[8]), .Z(clkcnt_31__N_559[8])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i9_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_6_i8_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[7]), 
         .D(tcr[7]), .Z(clkcnt_31__N_559[7])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i8_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_6_i3_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[2]), 
         .D(tcr[2]), .Z(clkcnt_31__N_559[2])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i3_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_6_i30_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[29]), 
         .D(tcr[29]), .Z(clkcnt_31__N_559[29])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i30_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_6_i29_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[28]), 
         .D(tcr[28]), .Z(clkcnt_31__N_559[28])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i29_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_6_i25_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[24]), 
         .D(tcr[24]), .Z(clkcnt_31__N_559[24])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i25_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_6_i24_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[23]), 
         .D(tcr[23]), .Z(clkcnt_31__N_559[23])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i24_3_lut_4_lut.init = 16'hf1e0;
    LUT4 mux_6_i7_3_lut_4_lut (.A(pwma_N_633), .B(clkcnt[31]), .C(n4[6]), 
         .D(tcr[6]), .Z(clkcnt_31__N_559[6])) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/full_brige_driver.v(83[23:33])
    defparam mux_6_i7_3_lut_4_lut.init = 16'hf1e0;
    CCU2D sub_295_add_2_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3825), .S0(pwma_N_632));
    defparam sub_295_add_2_cout.INIT0 = 16'h0000;
    defparam sub_295_add_2_cout.INIT1 = 16'h0000;
    defparam sub_295_add_2_cout.INJECT1_0 = "NO";
    defparam sub_295_add_2_cout.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_31 (.A0(hcr_r[29]), .B0(clkcnt[29]), .C0(GND_net), 
          .D0(GND_net), .A1(hcr_r[30]), .B1(clkcnt[30]), .C1(GND_net), 
          .D1(GND_net), .CIN(n3824), .COUT(n3825));
    defparam sub_295_add_2_31.INIT0 = 16'h5999;
    defparam sub_295_add_2_31.INIT1 = 16'h5999;
    defparam sub_295_add_2_31.INJECT1_0 = "NO";
    defparam sub_295_add_2_31.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_29 (.A0(hcr_r[27]), .B0(clkcnt[27]), .C0(GND_net), 
          .D0(GND_net), .A1(hcr_r[28]), .B1(clkcnt[28]), .C1(GND_net), 
          .D1(GND_net), .CIN(n3823), .COUT(n3824));
    defparam sub_295_add_2_29.INIT0 = 16'h5999;
    defparam sub_295_add_2_29.INIT1 = 16'h5999;
    defparam sub_295_add_2_29.INJECT1_0 = "NO";
    defparam sub_295_add_2_29.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_27 (.A0(hcr_r[25]), .B0(clkcnt[25]), .C0(GND_net), 
          .D0(GND_net), .A1(hcr_r[26]), .B1(clkcnt[26]), .C1(GND_net), 
          .D1(GND_net), .CIN(n3822), .COUT(n3823));
    defparam sub_295_add_2_27.INIT0 = 16'h5999;
    defparam sub_295_add_2_27.INIT1 = 16'h5999;
    defparam sub_295_add_2_27.INJECT1_0 = "NO";
    defparam sub_295_add_2_27.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_25 (.A0(hcr_r[23]), .B0(clkcnt[23]), .C0(GND_net), 
          .D0(GND_net), .A1(hcr_r[24]), .B1(clkcnt[24]), .C1(GND_net), 
          .D1(GND_net), .CIN(n3821), .COUT(n3822));
    defparam sub_295_add_2_25.INIT0 = 16'h5999;
    defparam sub_295_add_2_25.INIT1 = 16'h5999;
    defparam sub_295_add_2_25.INJECT1_0 = "NO";
    defparam sub_295_add_2_25.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_23 (.A0(hcr_r[21]), .B0(clkcnt[21]), .C0(GND_net), 
          .D0(GND_net), .A1(hcr_r[22]), .B1(clkcnt[22]), .C1(GND_net), 
          .D1(GND_net), .CIN(n3820), .COUT(n3821));
    defparam sub_295_add_2_23.INIT0 = 16'h5999;
    defparam sub_295_add_2_23.INIT1 = 16'h5999;
    defparam sub_295_add_2_23.INJECT1_0 = "NO";
    defparam sub_295_add_2_23.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_21 (.A0(hcr_r[19]), .B0(clkcnt[19]), .C0(GND_net), 
          .D0(GND_net), .A1(hcr_r[20]), .B1(clkcnt[20]), .C1(GND_net), 
          .D1(GND_net), .CIN(n3819), .COUT(n3820));
    defparam sub_295_add_2_21.INIT0 = 16'h5999;
    defparam sub_295_add_2_21.INIT1 = 16'h5999;
    defparam sub_295_add_2_21.INJECT1_0 = "NO";
    defparam sub_295_add_2_21.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_19 (.A0(hcr_r[17]), .B0(clkcnt[17]), .C0(GND_net), 
          .D0(GND_net), .A1(hcr_r[18]), .B1(clkcnt[18]), .C1(GND_net), 
          .D1(GND_net), .CIN(n3818), .COUT(n3819));
    defparam sub_295_add_2_19.INIT0 = 16'h5999;
    defparam sub_295_add_2_19.INIT1 = 16'h5999;
    defparam sub_295_add_2_19.INJECT1_0 = "NO";
    defparam sub_295_add_2_19.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_17 (.A0(hcr_r[15]), .B0(clkcnt[15]), .C0(GND_net), 
          .D0(GND_net), .A1(hcr_r[16]), .B1(clkcnt[16]), .C1(GND_net), 
          .D1(GND_net), .CIN(n3817), .COUT(n3818));
    defparam sub_295_add_2_17.INIT0 = 16'h5999;
    defparam sub_295_add_2_17.INIT1 = 16'h5999;
    defparam sub_295_add_2_17.INJECT1_0 = "NO";
    defparam sub_295_add_2_17.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_15 (.A0(hcr_r[13]), .B0(clkcnt[13]), .C0(GND_net), 
          .D0(GND_net), .A1(hcr_r[14]), .B1(clkcnt[14]), .C1(GND_net), 
          .D1(GND_net), .CIN(n3816), .COUT(n3817));
    defparam sub_295_add_2_15.INIT0 = 16'h5999;
    defparam sub_295_add_2_15.INIT1 = 16'h5999;
    defparam sub_295_add_2_15.INJECT1_0 = "NO";
    defparam sub_295_add_2_15.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_13 (.A0(hcr_r[11]), .B0(clkcnt[11]), .C0(GND_net), 
          .D0(GND_net), .A1(hcr_r[12]), .B1(clkcnt[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n3815), .COUT(n3816));
    defparam sub_295_add_2_13.INIT0 = 16'h5999;
    defparam sub_295_add_2_13.INIT1 = 16'h5999;
    defparam sub_295_add_2_13.INJECT1_0 = "NO";
    defparam sub_295_add_2_13.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_11 (.A0(hcr_r[9]), .B0(clkcnt[9]), .C0(GND_net), 
          .D0(GND_net), .A1(hcr_r[10]), .B1(clkcnt[10]), .C1(GND_net), 
          .D1(GND_net), .CIN(n3814), .COUT(n3815));
    defparam sub_295_add_2_11.INIT0 = 16'h5999;
    defparam sub_295_add_2_11.INIT1 = 16'h5999;
    defparam sub_295_add_2_11.INJECT1_0 = "NO";
    defparam sub_295_add_2_11.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_9 (.A0(hcr_r[7]), .B0(clkcnt[7]), .C0(GND_net), 
          .D0(GND_net), .A1(hcr_r[8]), .B1(clkcnt[8]), .C1(GND_net), 
          .D1(GND_net), .CIN(n3813), .COUT(n3814));
    defparam sub_295_add_2_9.INIT0 = 16'h5999;
    defparam sub_295_add_2_9.INIT1 = 16'h5999;
    defparam sub_295_add_2_9.INJECT1_0 = "NO";
    defparam sub_295_add_2_9.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_7 (.A0(hcr_r[5]), .B0(clkcnt[5]), .C0(GND_net), 
          .D0(GND_net), .A1(hcr_r[6]), .B1(clkcnt[6]), .C1(GND_net), 
          .D1(GND_net), .CIN(n3812), .COUT(n3813));
    defparam sub_295_add_2_7.INIT0 = 16'h5999;
    defparam sub_295_add_2_7.INIT1 = 16'h5999;
    defparam sub_295_add_2_7.INJECT1_0 = "NO";
    defparam sub_295_add_2_7.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_5 (.A0(hcr_r[3]), .B0(clkcnt[3]), .C0(GND_net), 
          .D0(GND_net), .A1(hcr_r[4]), .B1(clkcnt[4]), .C1(GND_net), 
          .D1(GND_net), .CIN(n3811), .COUT(n3812));
    defparam sub_295_add_2_5.INIT0 = 16'h5999;
    defparam sub_295_add_2_5.INIT1 = 16'h5999;
    defparam sub_295_add_2_5.INJECT1_0 = "NO";
    defparam sub_295_add_2_5.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_3 (.A0(hcr_r[1]), .B0(clkcnt[1]), .C0(GND_net), 
          .D0(GND_net), .A1(hcr_r[2]), .B1(clkcnt[2]), .C1(GND_net), 
          .D1(GND_net), .CIN(n3810), .COUT(n3811));
    defparam sub_295_add_2_3.INIT0 = 16'h5999;
    defparam sub_295_add_2_3.INIT1 = 16'h5999;
    defparam sub_295_add_2_3.INJECT1_0 = "NO";
    defparam sub_295_add_2_3.INJECT1_1 = "NO";
    CCU2D sub_295_add_2_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(hcr_r[0]), .B1(clkcnt[0]), .C1(GND_net), .D1(GND_net), 
          .COUT(n3810));
    defparam sub_295_add_2_1.INIT0 = 16'h0000;
    defparam sub_295_add_2_1.INIT1 = 16'h5999;
    defparam sub_295_add_2_1.INJECT1_0 = "NO";
    defparam sub_295_add_2_1.INJECT1_1 = "NO";
    
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

//
// Verilog Description of module Rst_sys
//

module Rst_sys (rst_n, clk_c, GND_net) /* synthesis syn_module_defined=1 */ ;
    output rst_n;
    input clk_c;
    input GND_net;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(3[8:11])
    
    wire n4612;
    wire [10:0]cnt;   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(30[25:28])
    
    wire cnt_10__N_288;
    wire [10:0]n49;
    
    wire n3799, n3800, n3797, n3798, n3796, n3613, n3575, n6;
    
    FD1S3AX rst_n_11 (.D(n4612), .CK(clk_c), .Q(rst_n)) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=10, LSE_RCOL=32, LSE_LLINE=15, LSE_RLINE=15 */ ;   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(40[7] 43[21])
    defparam rst_n_11.GSR = "DISABLED";
    FD1P3AX cnt_377__i0 (.D(n49[0]), .SP(cnt_10__N_288), .CK(clk_c), .Q(cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377__i0.GSR = "DISABLED";
    CCU2D cnt_377_add_4_9 (.A0(cnt[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3799), 
          .COUT(n3800), .S0(n49[7]), .S1(n49[8]));   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_377_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_377_add_4_9.INJECT1_0 = "NO";
    defparam cnt_377_add_4_9.INJECT1_1 = "NO";
    CCU2D cnt_377_add_4_5 (.A0(cnt[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3797), 
          .COUT(n3798), .S0(n49[3]), .S1(n49[4]));   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_377_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_377_add_4_5.INJECT1_0 = "NO";
    defparam cnt_377_add_4_5.INJECT1_1 = "NO";
    CCU2D cnt_377_add_4_3 (.A0(cnt[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3796), 
          .COUT(n3797), .S0(n49[1]), .S1(n49[2]));   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_377_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_377_add_4_3.INJECT1_0 = "NO";
    defparam cnt_377_add_4_3.INJECT1_1 = "NO";
    CCU2D cnt_377_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n3796), 
          .S1(n49[0]));   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377_add_4_1.INIT0 = 16'hF000;
    defparam cnt_377_add_4_1.INIT1 = 16'h0555;
    defparam cnt_377_add_4_1.INJECT1_0 = "NO";
    defparam cnt_377_add_4_1.INJECT1_1 = "NO";
    CCU2D cnt_377_add_4_11 (.A0(cnt[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3800), 
          .S0(n49[9]), .S1(n49[10]));   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_377_add_4_11.INIT1 = 16'hfaaa;
    defparam cnt_377_add_4_11.INJECT1_0 = "NO";
    defparam cnt_377_add_4_11.INJECT1_1 = "NO";
    LUT4 i2516_4_lut_rep_42 (.A(cnt[9]), .B(cnt[10]), .C(n3613), .D(cnt[8]), 
         .Z(n4612)) /* synthesis lut_function=(A (B)+!A (B (C+(D)))) */ ;
    defparam i2516_4_lut_rep_42.init = 16'hccc8;
    LUT4 i2517_1_lut_4_lut (.A(cnt[9]), .B(cnt[10]), .C(n3613), .D(cnt[8]), 
         .Z(cnt_10__N_288)) /* synthesis lut_function=(!(A (B)+!A (B (C+(D))))) */ ;
    defparam i2517_1_lut_4_lut.init = 16'h3337;
    FD1P3AX cnt_377__i1 (.D(n49[1]), .SP(cnt_10__N_288), .CK(clk_c), .Q(cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377__i1.GSR = "DISABLED";
    FD1P3AX cnt_377__i2 (.D(n49[2]), .SP(cnt_10__N_288), .CK(clk_c), .Q(cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377__i2.GSR = "DISABLED";
    FD1P3AX cnt_377__i3 (.D(n49[3]), .SP(cnt_10__N_288), .CK(clk_c), .Q(cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377__i3.GSR = "DISABLED";
    FD1P3AX cnt_377__i4 (.D(n49[4]), .SP(cnt_10__N_288), .CK(clk_c), .Q(cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377__i4.GSR = "DISABLED";
    FD1P3AX cnt_377__i5 (.D(n49[5]), .SP(cnt_10__N_288), .CK(clk_c), .Q(cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377__i5.GSR = "DISABLED";
    FD1P3AX cnt_377__i6 (.D(n49[6]), .SP(cnt_10__N_288), .CK(clk_c), .Q(cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377__i6.GSR = "DISABLED";
    FD1P3AX cnt_377__i7 (.D(n49[7]), .SP(cnt_10__N_288), .CK(clk_c), .Q(cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377__i7.GSR = "DISABLED";
    FD1P3AX cnt_377__i8 (.D(n49[8]), .SP(cnt_10__N_288), .CK(clk_c), .Q(cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377__i8.GSR = "DISABLED";
    FD1P3AX cnt_377__i9 (.D(n49[9]), .SP(cnt_10__N_288), .CK(clk_c), .Q(cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377__i9.GSR = "DISABLED";
    FD1P3AX cnt_377__i10 (.D(n49[10]), .SP(cnt_10__N_288), .CK(clk_c), 
            .Q(cnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377__i10.GSR = "DISABLED";
    LUT4 i2501_4_lut (.A(n3575), .B(cnt[7]), .C(cnt[6]), .D(cnt[5]), 
         .Z(n3613)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i2501_4_lut.init = 16'hc8c0;
    LUT4 i2464_4_lut (.A(cnt[0]), .B(cnt[4]), .C(n6), .D(cnt[3]), .Z(n3575)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;
    defparam i2464_4_lut.init = 16'heccc;
    LUT4 i2_2_lut (.A(cnt[1]), .B(cnt[2]), .Z(n6)) /* synthesis lut_function=(A (B)) */ ;
    defparam i2_2_lut.init = 16'h8888;
    CCU2D cnt_377_add_4_7 (.A0(cnt[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3798), 
          .COUT(n3799), .S0(n49[5]), .S1(n49[6]));   // f:/home/mini-step-fpga/prj/h_brige/rst_sys.v(35[12:19])
    defparam cnt_377_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_377_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_377_add_4_7.INJECT1_0 = "NO";
    defparam cnt_377_add_4_7.INJECT1_1 = "NO";
    
endmodule
//
// Verilog Description of module Debug_core
//

module Debug_core (clk_c, wr_data, rst_n, wr, tx_c, GND_net, rx_c, 
            valid_o, n4932, cmd, cmd_data, n4632, n4619, clk_c_enable_225, 
            clk_c_enable_147, clk_c_enable_296, n4627, n4332, clk_c_enable_265, 
            ope, clk_c_enable_216) /* synthesis syn_module_defined=1 */ ;
    input clk_c;
    input [31:0]wr_data;
    input rst_n;
    input wr;
    output tx_c;
    input GND_net;
    input rx_c;
    output valid_o;
    input n4932;
    output [7:0]cmd;
    output [31:0]cmd_data;
    output n4632;
    input n4619;
    output clk_c_enable_225;
    output clk_c_enable_147;
    output clk_c_enable_296;
    input n4627;
    input n4332;
    output clk_c_enable_265;
    input ope;
    output clk_c_enable_216;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(3[8:11])
    wire [31:0]tx_buf;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(455[12:18])
    
    wire clk_c_enable_116, n862, n861, n860, n859, n858, n857, 
        n856, n855, n854, n2572;
    wire [7:0]tdata;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(447[10:15])
    
    wire clk_c_enable_58, n863;
    wire [2:0]cnt;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(443[11:14])
    
    wire clk_c_enable_94;
    wire [2:0]cnt_2__N_651;
    
    wire n845, n4626;
    wire [12:0]r_shift_12__N_1014;
    
    wire n4647, n4646, n865, n866, n867, n864, n868, n869, n870, 
        n871, n4630, n872, start, tx_buf_31__N_760;
    wire [1:0]nstate;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(227[27:33])
    
    wire n873, n874, n4618, n875, n876, n877, n4221;
    wire [3:0]r_shift_cnt;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(232[17:28])
    wire [7:0]rx_data;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(438[18:25])
    
    wire n4634;
    wire [2:0]cnt_adj_1046;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(372[11:14])
    wire [2:0]cnt_2__N_963;
    
    wire cst, n4635, n28, n4616, clk_c_enable_177, n4625;
    
    FD1P3AX tx_buf_i0_i16 (.D(n862), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[16])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i16.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i15 (.D(n861), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[15])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i15.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i14 (.D(n860), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[14])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i14.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i13 (.D(n859), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[13])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i13.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i12 (.D(n858), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[12])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i12.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i11 (.D(n857), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[11])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i11.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i10 (.D(n856), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[10])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i10.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i9 (.D(n855), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[9])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i9.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i8 (.D(n854), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[8])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i8.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i1 (.D(wr_data[1]), .SP(clk_c_enable_116), .CD(n2572), 
            .CK(clk_c), .Q(tx_buf[1])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i1.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i2 (.D(wr_data[2]), .SP(clk_c_enable_116), .CD(n2572), 
            .CK(clk_c), .Q(tx_buf[2])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i2.GSR = "ENABLED";
    FD1P3AX tdata_i0_i0 (.D(tx_buf[24]), .SP(clk_c_enable_58), .CK(clk_c), 
            .Q(tdata[0])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i0.GSR = "DISABLED";
    FD1P3AX tx_buf_i0_i17 (.D(n863), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[17])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i17.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i3 (.D(wr_data[3]), .SP(clk_c_enable_116), .CD(n2572), 
            .CK(clk_c), .Q(tx_buf[3])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i3.GSR = "ENABLED";
    FD1P3AX cnt_i0 (.D(cnt_2__N_651[0]), .SP(clk_c_enable_94), .CK(clk_c), 
            .Q(cnt[0])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam cnt_i0.GSR = "ENABLED";
    LUT4 mux_111_i11_3_lut (.A(wr_data[10]), .B(tx_buf[2]), .C(n845), 
         .Z(n856)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i11_3_lut.init = 16'hcaca;
    LUT4 i1_3_lut_then_3_lut (.A(n4626), .B(r_shift_12__N_1014[12]), .C(cnt[0]), 
         .Z(n4647)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam i1_3_lut_then_3_lut.init = 16'h4040;
    FD1P3IX tx_buf_i0_i4 (.D(wr_data[4]), .SP(clk_c_enable_116), .CD(n2572), 
            .CK(clk_c), .Q(tx_buf[4])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i4.GSR = "ENABLED";
    LUT4 i122_2_lut (.A(n845), .B(rst_n), .Z(clk_c_enable_58)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam i122_2_lut.init = 16'h8888;
    FD1P3AX cnt_i2 (.D(cnt_2__N_651[2]), .SP(clk_c_enable_94), .CK(clk_c), 
            .Q(cnt[2])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam cnt_i2.GSR = "ENABLED";
    LUT4 i1_3_lut_else_3_lut (.A(n4626), .B(r_shift_12__N_1014[12]), .C(cnt[0]), 
         .D(cnt[2]), .Z(n4646)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;
    defparam i1_3_lut_else_3_lut.init = 16'h0400;
    LUT4 mux_111_i20_3_lut (.A(wr_data[19]), .B(tx_buf[11]), .C(n845), 
         .Z(n865)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i20_3_lut.init = 16'hcaca;
    LUT4 mux_111_i21_3_lut (.A(wr_data[20]), .B(tx_buf[12]), .C(n845), 
         .Z(n866)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i21_3_lut.init = 16'hcaca;
    LUT4 mux_111_i22_3_lut (.A(wr_data[21]), .B(tx_buf[13]), .C(n845), 
         .Z(n867)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i22_3_lut.init = 16'hcaca;
    FD1P3AX tx_buf_i0_i18 (.D(n864), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[18])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i18.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i5 (.D(wr_data[5]), .SP(clk_c_enable_116), .CD(n2572), 
            .CK(clk_c), .Q(tx_buf[5])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i5.GSR = "ENABLED";
    FD1P3AX tdata_i0_i7 (.D(tx_buf[31]), .SP(clk_c_enable_58), .CK(clk_c), 
            .Q(tdata[7])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i7.GSR = "DISABLED";
    FD1P3AX tdata_i0_i6 (.D(tx_buf[30]), .SP(clk_c_enable_58), .CK(clk_c), 
            .Q(tdata[6])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i6.GSR = "DISABLED";
    FD1P3AX tdata_i0_i5 (.D(tx_buf[29]), .SP(clk_c_enable_58), .CK(clk_c), 
            .Q(tdata[5])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i5.GSR = "DISABLED";
    FD1P3AX tdata_i0_i4 (.D(tx_buf[28]), .SP(clk_c_enable_58), .CK(clk_c), 
            .Q(tdata[4])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i4.GSR = "DISABLED";
    FD1P3AX tdata_i0_i3 (.D(tx_buf[27]), .SP(clk_c_enable_58), .CK(clk_c), 
            .Q(tdata[3])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i3.GSR = "DISABLED";
    FD1P3AX tdata_i0_i2 (.D(tx_buf[26]), .SP(clk_c_enable_58), .CK(clk_c), 
            .Q(tdata[2])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i2.GSR = "DISABLED";
    FD1P3AX tdata_i0_i1 (.D(tx_buf[25]), .SP(clk_c_enable_58), .CK(clk_c), 
            .Q(tdata[1])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i1.GSR = "DISABLED";
    LUT4 mux_111_i23_3_lut (.A(wr_data[22]), .B(tx_buf[14]), .C(n845), 
         .Z(n868)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i23_3_lut.init = 16'hcaca;
    LUT4 mux_111_i24_3_lut (.A(wr_data[23]), .B(tx_buf[15]), .C(n845), 
         .Z(n869)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i24_3_lut.init = 16'hcaca;
    LUT4 mux_111_i25_3_lut (.A(wr_data[24]), .B(tx_buf[16]), .C(n845), 
         .Z(n870)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i25_3_lut.init = 16'hcaca;
    LUT4 mux_111_i26_3_lut (.A(wr_data[25]), .B(tx_buf[17]), .C(n845), 
         .Z(n871)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i26_3_lut.init = 16'hcaca;
    LUT4 i1_2_lut_rep_60 (.A(cnt[0]), .B(cnt[1]), .Z(n4630)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(452[18:29])
    defparam i1_2_lut_rep_60.init = 16'heeee;
    LUT4 mux_111_i27_3_lut (.A(wr_data[26]), .B(tx_buf[18]), .C(n845), 
         .Z(n872)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i27_3_lut.init = 16'hcaca;
    LUT4 i307_4_lut (.A(start), .B(wr), .C(tx_buf_31__N_760), .D(nstate[1]), 
         .Z(clk_c_enable_116)) /* synthesis lut_function=(!(A ((C)+!B)+!A (B (C (D))+!B ((D)+!C)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam i307_4_lut.init = 16'h0c5c;
    LUT4 mux_111_i28_3_lut (.A(wr_data[27]), .B(tx_buf[19]), .C(n845), 
         .Z(n873)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i28_3_lut.init = 16'hcaca;
    LUT4 mux_111_i29_3_lut (.A(wr_data[28]), .B(tx_buf[20]), .C(n845), 
         .Z(n874)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i29_3_lut.init = 16'hcaca;
    LUT4 i1_2_lut_4_lut_4_lut (.A(cnt[0]), .B(cnt[1]), .C(cnt[2]), .D(n4618), 
         .Z(cnt_2__N_651[0])) /* synthesis lut_function=(!(A+!(B (D)+!B (C (D))))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(452[18:29])
    defparam i1_2_lut_4_lut_4_lut.init = 16'h5400;
    LUT4 mux_111_i30_3_lut (.A(wr_data[29]), .B(tx_buf[21]), .C(n845), 
         .Z(n875)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i30_3_lut.init = 16'hcaca;
    LUT4 mux_111_i31_3_lut (.A(wr_data[30]), .B(tx_buf[22]), .C(n845), 
         .Z(n876)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i31_3_lut.init = 16'hcaca;
    LUT4 mux_111_i32_3_lut (.A(wr_data[31]), .B(tx_buf[23]), .C(n845), 
         .Z(n877)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i32_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut (.A(start), .B(tx_buf_31__N_760), .C(n4221), .D(r_shift_12__N_1014[12]), 
         .Z(n845)) /* synthesis lut_function=(!(A+!(B (C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam i1_4_lut.init = 16'h4044;
    LUT4 i1_4_lut_adj_66 (.A(r_shift_cnt[0]), .B(r_shift_cnt[3]), .C(r_shift_cnt[1]), 
         .D(r_shift_cnt[2]), .Z(n4221)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam i1_4_lut_adj_66.init = 16'h0040;
    FD1S3AY start_30 (.D(n845), .CK(clk_c), .Q(start));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam start_30.GSR = "ENABLED";
    LUT4 i1_2_lut (.A(cnt[2]), .B(cnt[1]), .Z(tx_buf_31__N_760)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam i1_2_lut.init = 16'heeee;
    FD1P3IX tx_buf_i0_i0 (.D(wr_data[0]), .SP(clk_c_enable_116), .CD(n2572), 
            .CK(clk_c), .Q(tx_buf[0])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i0.GSR = "ENABLED";
    FD1P3AX cnt_i1 (.D(cnt_2__N_651[1]), .SP(clk_c_enable_94), .CK(clk_c), 
            .Q(cnt[1])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam cnt_i1.GSR = "ENABLED";
    LUT4 mux_111_i15_3_lut (.A(wr_data[14]), .B(tx_buf[6]), .C(n845), 
         .Z(n860)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i15_3_lut.init = 16'hcaca;
    FD1P3IX tx_buf_i0_i6 (.D(wr_data[6]), .SP(clk_c_enable_116), .CD(n2572), 
            .CK(clk_c), .Q(tx_buf[6])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i6.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i7 (.D(wr_data[7]), .SP(clk_c_enable_116), .CD(n2572), 
            .CK(clk_c), .Q(tx_buf[7])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i7.GSR = "ENABLED";
    LUT4 mux_111_i14_3_lut (.A(wr_data[13]), .B(tx_buf[5]), .C(n845), 
         .Z(n859)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i14_3_lut.init = 16'hcaca;
    LUT4 mux_111_i13_3_lut (.A(wr_data[12]), .B(tx_buf[4]), .C(n845), 
         .Z(n858)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i13_3_lut.init = 16'hcaca;
    FD1P3AX tx_buf_i0_i19 (.D(n865), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[19])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i19.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i20 (.D(n866), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[20])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i20.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i21 (.D(n867), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[21])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i21.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i22 (.D(n868), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[22])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i22.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i23 (.D(n869), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[23])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i23.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i24 (.D(n870), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[24])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i24.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i25 (.D(n871), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[25])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i25.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i26 (.D(n872), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[26])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i26.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i27 (.D(n873), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[27])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i27.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i28 (.D(n874), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[28])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i28.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i29 (.D(n875), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[29])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i29.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i30 (.D(n876), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[30])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i30.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i31 (.D(n877), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tx_buf[31])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=83, LSE_RLINE=94 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i31.GSR = "ENABLED";
    LUT4 mux_111_i17_3_lut (.A(wr_data[16]), .B(tx_buf[8]), .C(n845), 
         .Z(n862)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i17_3_lut.init = 16'hcaca;
    LUT4 mux_111_i16_3_lut (.A(wr_data[15]), .B(tx_buf[7]), .C(n845), 
         .Z(n861)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i16_3_lut.init = 16'hcaca;
    LUT4 mux_111_i10_3_lut (.A(wr_data[9]), .B(tx_buf[1]), .C(n845), .Z(n855)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i10_3_lut.init = 16'hcaca;
    LUT4 mux_111_i9_3_lut (.A(wr_data[8]), .B(tx_buf[0]), .C(n845), .Z(n854)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i9_3_lut.init = 16'hcaca;
    LUT4 mux_111_i18_3_lut (.A(wr_data[17]), .B(tx_buf[9]), .C(n845), 
         .Z(n863)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i18_3_lut.init = 16'hcaca;
    LUT4 i3222_3_lut_4_lut (.A(r_shift_12__N_1014[12]), .B(n4626), .C(cnt[2]), 
         .D(n4630), .Z(cnt_2__N_651[2])) /* synthesis lut_function=((B+(C (D)))+!A) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(477[9] 479[12])
    defparam i3222_3_lut_4_lut.init = 16'hfddd;
    LUT4 i1_3_lut_4_lut (.A(r_shift_12__N_1014[12]), .B(n4626), .C(tx_buf_31__N_760), 
         .D(wr), .Z(clk_c_enable_94)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A (C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(477[9] 479[12])
    defparam i1_3_lut_4_lut.init = 16'h2f22;
    LUT4 i1478_2_lut (.A(clk_c_enable_116), .B(n845), .Z(n2572)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(462[10] 480[8])
    defparam i1478_2_lut.init = 16'h8888;
    LUT4 mux_111_i12_3_lut (.A(wr_data[11]), .B(tx_buf[3]), .C(n845), 
         .Z(n857)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i12_3_lut.init = 16'hcaca;
    LUT4 mux_111_i19_3_lut (.A(wr_data[18]), .B(tx_buf[10]), .C(n845), 
         .Z(n864)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(471[14] 474[12])
    defparam mux_111_i19_3_lut.init = 16'hcaca;
    PFUMX i3264 (.BLUT(n4646), .ALUT(n4647), .C0(cnt[1]), .Z(cnt_2__N_651[1]));
    Debug_core_uart_tx Debug_core_uart_tx_uut (.clk_c(clk_c), .r_shift_cnt({r_shift_cnt}), 
            .start(start), .\r_shift_12__N_1014[12] (r_shift_12__N_1014[12]), 
            .n4626(n4626), .\nstate[1] (nstate[1]), .tx_c(tx_c), .tdata({tdata}), 
            .n4618(n4618), .GND_net(GND_net)) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(507[3] 515[2])
    Debug_core_uart_rx Debug_core_uart_rx_uut (.clk_c(clk_c), .rx_data({rx_data}), 
            .rx_c(rx_c), .GND_net(GND_net), .n4634(n4634), .\cnt[1] (cnt_adj_1046[1]), 
            .\cnt[0] (cnt_adj_1046[0]), .\cnt_2__N_963[1] (cnt_2__N_963[1]), 
            .cst(cst), .n4635(n4635), .n28(n28), .n4616(n4616), .clk_c_enable_177(clk_c_enable_177), 
            .n4625(n4625), .\cnt_2__N_963[0] (cnt_2__N_963[0])) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(486[3] 492[2])
    Debug_core_DecodeUart Debug_core_DecodeUart_uut (.valid_o(valid_o), .clk_c(clk_c), 
            .n4932(n4932), .cnt({Open_0, cnt_adj_1046[1:0]}), .n4634(n4634), 
            .cmd({cmd}), .rx_data({rx_data}), .cmd_data({cmd_data}), .cst(cst), 
            .rst_n(rst_n), .n4632(n4632), .n4619(n4619), .clk_c_enable_225(clk_c_enable_225), 
            .clk_c_enable_147(clk_c_enable_147), .clk_c_enable_296(clk_c_enable_296), 
            .n4625(n4625), .n4627(n4627), .n4332(n4332), .clk_c_enable_265(clk_c_enable_265), 
            .ope(ope), .clk_c_enable_216(clk_c_enable_216), .\cnt_2__N_963[0] (cnt_2__N_963[0]), 
            .n4616(n4616), .\cnt_2__N_963[1] (cnt_2__N_963[1]), .clk_c_enable_177(clk_c_enable_177), 
            .n4635(n4635), .n28(n28)) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(494[23] 502[2])
    
endmodule
//
// Verilog Description of module Debug_core_uart_tx
//

module Debug_core_uart_tx (clk_c, r_shift_cnt, start, \r_shift_12__N_1014[12] , 
            n4626, \nstate[1] , tx_c, tdata, n4618, GND_net) /* synthesis syn_module_defined=1 */ ;
    input clk_c;
    output [3:0]r_shift_cnt;
    input start;
    output \r_shift_12__N_1014[12] ;
    output n4626;
    output \nstate[1] ;
    output tx_c;
    input [7:0]tdata;
    output n4618;
    input GND_net;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(3[8:11])
    wire [12:0]r_shift;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(233[18:25])
    
    wire clk_c_enable_234, n2604;
    wire [12:0]r_shift_12__N_1014;
    
    wire n2363, n4628;
    wire [6:0]r_hold_cnt;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(234[34:44])
    
    wire n4641, n4640, n4929, n4621, n4930, n4338, r_tx_order_buf, 
        n4629;
    wire [12:0]r_shift_12__N_987;
    
    wire r_shift_cnt_3__N_1013;
    wire [3:0]n21;
    wire [6:0]n33;
    
    wire clk_c_enable_233, n4637, n4642, n4242, n3808, n3807, n3806;
    
    FD1P3JX r_shift_i12 (.D(r_shift_12__N_1014[11]), .SP(clk_c_enable_234), 
            .PD(n2604), .CK(clk_c), .Q(r_shift[11])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(296[9] 330[12])
    defparam r_shift_i12.GSR = "ENABLED";
    FD1P3JX r_shift_i11 (.D(r_shift_12__N_1014[10]), .SP(clk_c_enable_234), 
            .PD(n2604), .CK(clk_c), .Q(r_shift[10])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(296[9] 330[12])
    defparam r_shift_i11.GSR = "ENABLED";
    LUT4 i2662_2_lut_3_lut_4_lut_4_lut_then_4_lut (.A(n2363), .B(n4628), 
         .C(r_hold_cnt[1]), .D(r_shift_cnt[1]), .Z(n4641)) /* synthesis lut_function=(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (D)+!B ((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(314[10] 322[8])
    defparam i2662_2_lut_3_lut_4_lut_4_lut_then_4_lut.init = 16'hdf21;
    LUT4 i2662_2_lut_3_lut_4_lut_4_lut_else_4_lut (.A(n2363), .B(n4628), 
         .C(r_hold_cnt[1]), .D(r_shift_cnt[1]), .Z(n4640)) /* synthesis lut_function=(A (D)+!A (B (D)+!B ((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(314[10] 322[8])
    defparam i2662_2_lut_3_lut_4_lut_4_lut_else_4_lut.init = 16'hff01;
    LUT4 i2_3_lut_rep_70 (.A(n4628), .B(n2363), .C(r_hold_cnt[1]), .Z(n4929)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(306[10:37])
    defparam i2_3_lut_rep_70.init = 16'hfefe;
    LUT4 n4628_bdd_4_lut (.A(r_shift_cnt[0]), .B(r_shift_cnt[1]), .C(r_shift_cnt[2]), 
         .D(n4621), .Z(n4930)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;
    defparam n4628_bdd_4_lut.init = 16'h78f0;
    LUT4 i2_3_lut_rep_58 (.A(n4338), .B(r_hold_cnt[4]), .C(r_hold_cnt[3]), 
         .Z(n4628)) /* synthesis lut_function=((B+(C))+!A) */ ;
    defparam i2_3_lut_rep_58.init = 16'hfdfd;
    LUT4 i1_2_lut_rep_51_4_lut (.A(n4338), .B(r_hold_cnt[4]), .C(r_hold_cnt[3]), 
         .D(r_hold_cnt[1]), .Z(n4621)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
    defparam i1_2_lut_rep_51_4_lut.init = 16'h0200;
    LUT4 start_I_0_2_lut_rep_59 (.A(start), .B(r_tx_order_buf), .Z(n4629)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(241[29:54])
    defparam start_I_0_2_lut_rep_59.init = 16'h2222;
    LUT4 i2195_3_lut_4_lut (.A(start), .B(r_tx_order_buf), .C(\r_shift_12__N_1014[12] ), 
         .D(r_shift[1]), .Z(r_shift_12__N_987[0])) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A ((D)+!C)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(241[29:54])
    defparam i2195_3_lut_4_lut.init = 16'hfd0d;
    LUT4 mux_706_i1_3_lut_4_lut (.A(start), .B(r_tx_order_buf), .C(\r_shift_12__N_1014[12] ), 
         .D(n4626), .Z(\nstate[1] )) /* synthesis lut_function=(A (B (C (D))+!B ((D)+!C))+!A (C (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(241[29:54])
    defparam mux_706_i1_3_lut_4_lut.init = 16'hf202;
    FD1S3AX cstate_i1 (.D(\nstate[1] ), .CK(clk_c), .Q(\r_shift_12__N_1014[12] )) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(262[13:30])
    defparam cstate_i1.GSR = "ENABLED";
    LUT4 i2258_2_lut_3_lut (.A(start), .B(r_tx_order_buf), .C(\r_shift_12__N_1014[12] ), 
         .Z(r_shift_12__N_987[12])) /* synthesis lut_function=(A ((C)+!B)+!A (C)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(241[29:54])
    defparam i2258_2_lut_3_lut.init = 16'hf2f2;
    FD1P3AY r_shift_i1 (.D(r_shift_12__N_987[0]), .SP(clk_c_enable_234), 
            .CK(clk_c), .Q(tx_c)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(296[9] 330[12])
    defparam r_shift_i1.GSR = "ENABLED";
    FD1S3AX r_tx_order_buf_57 (.D(start), .CK(clk_c), .Q(r_tx_order_buf)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(250[9] 253[12])
    defparam r_tx_order_buf_57.GSR = "ENABLED";
    FD1S3IX r_shift_cnt_376__i0 (.D(n21[0]), .CK(clk_c), .CD(r_shift_cnt_3__N_1013), 
            .Q(r_shift_cnt[0]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(314[10] 322[8])
    defparam r_shift_cnt_376__i0.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_383__i0 (.D(n33[0]), .CK(clk_c), .CD(clk_c_enable_234), 
            .Q(r_hold_cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(321[26:43])
    defparam r_hold_cnt_383__i0.GSR = "ENABLED";
    LUT4 r_shift_12__I_0_i2_4_lut (.A(tdata[0]), .B(r_shift[2]), .C(\r_shift_12__N_1014[12] ), 
         .D(n4629), .Z(r_shift_12__N_987[1])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i2_4_lut.init = 16'hcacf;
    LUT4 r_shift_12__I_0_i3_4_lut (.A(tdata[1]), .B(r_shift[3]), .C(\r_shift_12__N_1014[12] ), 
         .D(n4629), .Z(r_shift_12__N_987[2])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i3_4_lut.init = 16'hcacf;
    LUT4 r_shift_12__I_0_i4_4_lut (.A(tdata[2]), .B(r_shift[4]), .C(\r_shift_12__N_1014[12] ), 
         .D(n4629), .Z(r_shift_12__N_987[3])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i4_4_lut.init = 16'hcacf;
    LUT4 i2654_2_lut_3_lut_4_lut (.A(n2363), .B(n4621), .C(n4929), .D(r_shift_cnt[0]), 
         .Z(n21[0])) /* synthesis lut_function=(!(A (B (C (D))+!B !(C (D)))+!A !(C (D)))) */ ;
    defparam i2654_2_lut_3_lut_4_lut.init = 16'h7888;
    FD1S3IX r_hold_cnt_383__i1 (.D(n33[1]), .CK(clk_c), .CD(clk_c_enable_234), 
            .Q(r_hold_cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(321[26:43])
    defparam r_hold_cnt_383__i1.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_383__i2 (.D(n33[2]), .CK(clk_c), .CD(clk_c_enable_234), 
            .Q(r_hold_cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(321[26:43])
    defparam r_hold_cnt_383__i2.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_383__i3 (.D(n33[3]), .CK(clk_c), .CD(clk_c_enable_234), 
            .Q(r_hold_cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(321[26:43])
    defparam r_hold_cnt_383__i3.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_383__i4 (.D(n33[4]), .CK(clk_c), .CD(clk_c_enable_234), 
            .Q(r_hold_cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(321[26:43])
    defparam r_hold_cnt_383__i4.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_383__i5 (.D(n33[5]), .CK(clk_c), .CD(clk_c_enable_234), 
            .Q(r_hold_cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(321[26:43])
    defparam r_hold_cnt_383__i5.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_383__i6 (.D(n33[6]), .CK(clk_c), .CD(clk_c_enable_234), 
            .Q(r_hold_cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(321[26:43])
    defparam r_hold_cnt_383__i6.GSR = "ENABLED";
    FD1P3AY r_shift_i2 (.D(r_shift_12__N_987[1]), .SP(clk_c_enable_234), 
            .CK(clk_c), .Q(r_shift[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(296[9] 330[12])
    defparam r_shift_i2.GSR = "ENABLED";
    LUT4 r_shift_12__I_0_i5_4_lut (.A(tdata[3]), .B(r_shift[5]), .C(\r_shift_12__N_1014[12] ), 
         .D(n4629), .Z(r_shift_12__N_987[4])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i5_4_lut.init = 16'hcacf;
    FD1P3AY r_shift_i3 (.D(r_shift_12__N_987[2]), .SP(clk_c_enable_234), 
            .CK(clk_c), .Q(r_shift[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(296[9] 330[12])
    defparam r_shift_i3.GSR = "ENABLED";
    FD1P3AY r_shift_i4 (.D(r_shift_12__N_987[3]), .SP(clk_c_enable_234), 
            .CK(clk_c), .Q(r_shift[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(296[9] 330[12])
    defparam r_shift_i4.GSR = "ENABLED";
    FD1P3AY r_shift_i5 (.D(r_shift_12__N_987[4]), .SP(clk_c_enable_234), 
            .CK(clk_c), .Q(r_shift[4])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(296[9] 330[12])
    defparam r_shift_i5.GSR = "ENABLED";
    FD1P3AY r_shift_i6 (.D(r_shift_12__N_987[5]), .SP(clk_c_enable_234), 
            .CK(clk_c), .Q(r_shift[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(296[9] 330[12])
    defparam r_shift_i6.GSR = "ENABLED";
    FD1P3AY r_shift_i7 (.D(r_shift_12__N_987[6]), .SP(clk_c_enable_234), 
            .CK(clk_c), .Q(r_shift[6])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(296[9] 330[12])
    defparam r_shift_i7.GSR = "ENABLED";
    FD1P3AY r_shift_i8 (.D(r_shift_12__N_987[7]), .SP(clk_c_enable_234), 
            .CK(clk_c), .Q(r_shift[7])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(296[9] 330[12])
    defparam r_shift_i8.GSR = "ENABLED";
    FD1P3AY r_shift_i9 (.D(r_shift_12__N_987[8]), .SP(clk_c_enable_234), 
            .CK(clk_c), .Q(r_shift[8])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(296[9] 330[12])
    defparam r_shift_i9.GSR = "ENABLED";
    FD1P3JX r_shift_i10 (.D(r_shift[10]), .SP(clk_c_enable_233), .PD(r_shift_cnt_3__N_1013), 
            .CK(clk_c), .Q(r_shift[9])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(296[9] 330[12])
    defparam r_shift_i10.GSR = "ENABLED";
    FD1P3AY r_shift_i13 (.D(r_shift_12__N_987[12]), .SP(clk_c_enable_234), 
            .CK(clk_c), .Q(r_shift[12])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(296[9] 330[12])
    defparam r_shift_i13.GSR = "ENABLED";
    LUT4 r_shift_12__I_0_i6_4_lut (.A(tdata[4]), .B(r_shift[6]), .C(\r_shift_12__N_1014[12] ), 
         .D(n4629), .Z(r_shift_12__N_987[5])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i6_4_lut.init = 16'hcacf;
    LUT4 i1_2_lut_rep_67 (.A(r_shift_cnt[2]), .B(r_shift_cnt[3]), .Z(n4637)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(305[10:27])
    defparam i1_2_lut_rep_67.init = 16'hbbbb;
    LUT4 i2_3_lut_rep_56_4_lut (.A(r_shift_cnt[2]), .B(r_shift_cnt[3]), 
         .C(r_shift_cnt[1]), .D(r_shift_cnt[0]), .Z(n4626)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(305[10:27])
    defparam i2_3_lut_rep_56_4_lut.init = 16'hffbf;
    FD1S3IX r_shift_cnt_376__i1 (.D(n4642), .CK(clk_c), .CD(r_shift_cnt_3__N_1013), 
            .Q(r_shift_cnt[1]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(314[10] 322[8])
    defparam r_shift_cnt_376__i1.GSR = "ENABLED";
    LUT4 i2_3_lut_4_lut (.A(r_shift_cnt[2]), .B(r_shift_cnt[3]), .C(r_shift_cnt[1]), 
         .D(r_shift_cnt[0]), .Z(n2363)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(305[10:27])
    defparam i2_3_lut_4_lut.init = 16'hfbff;
    LUT4 r_shift_12__I_0_i7_4_lut (.A(tdata[5]), .B(r_shift[7]), .C(\r_shift_12__N_1014[12] ), 
         .D(n4629), .Z(r_shift_12__N_987[6])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i7_4_lut.init = 16'hcacf;
    LUT4 i2_3_lut (.A(r_tx_order_buf), .B(start), .C(\r_shift_12__N_1014[12] ), 
         .Z(n2604)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(296[9] 330[12])
    defparam i2_3_lut.init = 16'h0404;
    FD1S3IX r_shift_cnt_376__i2 (.D(n4930), .CK(clk_c), .CD(r_shift_cnt_3__N_1013), 
            .Q(r_shift_cnt[2]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(314[10] 322[8])
    defparam r_shift_cnt_376__i2.GSR = "ENABLED";
    FD1S3IX r_shift_cnt_376__i3 (.D(n21[3]), .CK(clk_c), .CD(r_shift_cnt_3__N_1013), 
            .Q(r_shift_cnt[3]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(314[10] 322[8])
    defparam r_shift_cnt_376__i3.GSR = "ENABLED";
    LUT4 i2257_2_lut (.A(r_shift[12]), .B(\r_shift_12__N_1014[12] ), .Z(r_shift_12__N_1014[11])) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(325[13] 329[16])
    defparam i2257_2_lut.init = 16'h8888;
    LUT4 i3201_2_lut_4_lut (.A(n4628), .B(r_hold_cnt[1]), .C(n2363), .D(\r_shift_12__N_1014[12] ), 
         .Z(clk_c_enable_234)) /* synthesis lut_function=(!(A (D)+!A !(B (C+!(D))+!B !(C (D))))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(315[10:40])
    defparam i3201_2_lut_4_lut.init = 16'h41ff;
    LUT4 r_shift_12__I_0_i8_4_lut (.A(tdata[6]), .B(r_shift[8]), .C(\r_shift_12__N_1014[12] ), 
         .D(n4629), .Z(r_shift_12__N_987[7])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i8_4_lut.init = 16'hcacf;
    LUT4 r_shift_12__I_0_i9_4_lut (.A(tdata[7]), .B(r_shift[9]), .C(\r_shift_12__N_1014[12] ), 
         .D(n4629), .Z(r_shift_12__N_987[8])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i9_4_lut.init = 16'hcacf;
    LUT4 i1_2_lut_rep_48_4_lut (.A(n4637), .B(r_shift_cnt[0]), .C(r_shift_cnt[1]), 
         .D(\r_shift_12__N_1014[12] ), .Z(n4618)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(305[10:27])
    defparam i1_2_lut_rep_48_4_lut.init = 16'h1000;
    LUT4 i3162_4_lut (.A(r_hold_cnt[0]), .B(r_hold_cnt[5]), .C(r_hold_cnt[2]), 
         .D(r_hold_cnt[6]), .Z(n4338)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i3162_4_lut.init = 16'h8000;
    LUT4 i2676_3_lut (.A(r_shift_cnt[3]), .B(n4242), .C(n4929), .Z(n21[3])) /* synthesis lut_function=(!(A (B)+!A !(B (C)+!B !(C)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(314[10] 322[8])
    defparam i2676_3_lut.init = 16'h6363;
    LUT4 i3_4_lut (.A(r_shift_cnt[2]), .B(r_shift_cnt[0]), .C(r_shift_cnt[1]), 
         .D(n4621), .Z(n4242)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(314[10] 322[8])
    defparam i3_4_lut.init = 16'h8000;
    LUT4 i2256_2_lut (.A(r_shift[11]), .B(\r_shift_12__N_1014[12] ), .Z(r_shift_12__N_1014[10])) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(325[13] 329[16])
    defparam i2256_2_lut.init = 16'h8888;
    LUT4 i1_1_lut (.A(\r_shift_12__N_1014[12] ), .Z(r_shift_cnt_3__N_1013)) /* synthesis lut_function=(!(A)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(296[9] 330[12])
    defparam i1_1_lut.init = 16'h5555;
    LUT4 i3207_3_lut_rep_54 (.A(n4628), .B(r_hold_cnt[1]), .C(n2363), 
         .Z(clk_c_enable_233)) /* synthesis lut_function=(!(A+!(B (C)+!B !(C)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(315[10:40])
    defparam i3207_3_lut_rep_54.init = 16'h4141;
    CCU2D r_hold_cnt_383_add_4_7 (.A0(r_hold_cnt[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(r_hold_cnt[6]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3808), .S0(n33[5]), .S1(n33[6]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(321[26:43])
    defparam r_hold_cnt_383_add_4_7.INIT0 = 16'hfaaa;
    defparam r_hold_cnt_383_add_4_7.INIT1 = 16'hfaaa;
    defparam r_hold_cnt_383_add_4_7.INJECT1_0 = "NO";
    defparam r_hold_cnt_383_add_4_7.INJECT1_1 = "NO";
    CCU2D r_hold_cnt_383_add_4_5 (.A0(r_hold_cnt[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(r_hold_cnt[4]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3807), .COUT(n3808), .S0(n33[3]), .S1(n33[4]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(321[26:43])
    defparam r_hold_cnt_383_add_4_5.INIT0 = 16'hfaaa;
    defparam r_hold_cnt_383_add_4_5.INIT1 = 16'hfaaa;
    defparam r_hold_cnt_383_add_4_5.INJECT1_0 = "NO";
    defparam r_hold_cnt_383_add_4_5.INJECT1_1 = "NO";
    CCU2D r_hold_cnt_383_add_4_3 (.A0(r_hold_cnt[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(r_hold_cnt[2]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3806), .COUT(n3807), .S0(n33[1]), .S1(n33[2]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(321[26:43])
    defparam r_hold_cnt_383_add_4_3.INIT0 = 16'hfaaa;
    defparam r_hold_cnt_383_add_4_3.INIT1 = 16'hfaaa;
    defparam r_hold_cnt_383_add_4_3.INJECT1_0 = "NO";
    defparam r_hold_cnt_383_add_4_3.INJECT1_1 = "NO";
    CCU2D r_hold_cnt_383_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(r_hold_cnt[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n3806), .S1(n33[0]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(321[26:43])
    defparam r_hold_cnt_383_add_4_1.INIT0 = 16'hF000;
    defparam r_hold_cnt_383_add_4_1.INIT1 = 16'h0555;
    defparam r_hold_cnt_383_add_4_1.INJECT1_0 = "NO";
    defparam r_hold_cnt_383_add_4_1.INJECT1_1 = "NO";
    PFUMX i3260 (.BLUT(n4640), .ALUT(n4641), .C0(r_shift_cnt[0]), .Z(n4642));
    
endmodule
//
// Verilog Description of module Debug_core_uart_rx
//

module Debug_core_uart_rx (clk_c, rx_data, rx_c, GND_net, n4634, \cnt[1] , 
            \cnt[0] , \cnt_2__N_963[1] , cst, n4635, n28, n4616, 
            clk_c_enable_177, n4625, \cnt_2__N_963[0] ) /* synthesis syn_module_defined=1 */ ;
    input clk_c;
    output [7:0]rx_data;
    input rx_c;
    input GND_net;
    output n4634;
    input \cnt[1] ;
    input \cnt[0] ;
    output \cnt_2__N_963[1] ;
    input cst;
    input n4635;
    output n28;
    input n4616;
    output clk_c_enable_177;
    output n4625;
    output \cnt_2__N_963[0] ;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(3[8:11])
    wire [2:0]n1384;
    wire [1:0]nstate_1__N_801;
    
    wire n1861;
    wire [6:0]r_sample_cnt;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(62[34:46])
    
    wire n4600;
    wire [3:0]r_shift_cnt;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(69[17:28])
    
    wire clk_c_enable_66, n2583, n3925, n13, n3874, n6;
    wire [1:0]nstate_1__N_799;
    
    wire clk_c_enable_36;
    wire [9:0]r_shift;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(70[17:24])
    
    wire r_uart_rx_falling_N_875, clk_c_enable_224, n2597;
    wire [6:0]n33;
    
    wire busy_f, busy, r_uart_rx_buf, clk_c_enable_223, n1838, n3802, 
        n3803;
    wire [3:0]n21;
    
    wire n4602, n4623, n9, n4310, n3804;
    
    LUT4 i752_2_lut (.A(n1384[0]), .B(nstate_1__N_801[0]), .Z(n1861)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(111[9] 126[17])
    defparam i752_2_lut.init = 16'h2222;
    LUT4 n3874_bdd_4_lut_3323 (.A(r_sample_cnt[4]), .B(r_sample_cnt[6]), 
         .C(r_sample_cnt[3]), .D(r_sample_cnt[2]), .Z(n4600)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;
    defparam n3874_bdd_4_lut_3323.init = 16'h0400;
    FD1P3IX r_shift_cnt_379__i0 (.D(n3925), .SP(clk_c_enable_66), .CD(n2583), 
            .CK(clk_c), .Q(r_shift_cnt[0]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(146[36:54])
    defparam r_shift_cnt_379__i0.GSR = "ENABLED";
    LUT4 i1_2_lut (.A(n13), .B(r_shift_cnt[0]), .Z(n3925)) /* synthesis lut_function=(A (B)+!A !(B)) */ ;
    defparam i1_2_lut.init = 16'h9999;
    LUT4 i4_4_lut (.A(r_sample_cnt[4]), .B(n3874), .C(r_sample_cnt[6]), 
         .D(n6), .Z(n13)) /* synthesis lut_function=(((C+(D))+!B)+!A) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(151[8:38])
    defparam i4_4_lut.init = 16'hfff7;
    LUT4 i2_4_lut (.A(r_shift_cnt[1]), .B(r_shift_cnt[0]), .C(r_shift_cnt[3]), 
         .D(r_shift_cnt[2]), .Z(nstate_1__N_799[0])) /* synthesis lut_function=((B+((D)+!C))+!A) */ ;
    defparam i2_4_lut.init = 16'hffdf;
    FD1P3AX r_rx_data_i0_i0 (.D(r_shift[1]), .SP(clk_c_enable_36), .CK(clk_c), 
            .Q(rx_data[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i0.GSR = "ENABLED";
    LUT4 i1_2_lut_adj_65 (.A(r_sample_cnt[3]), .B(r_sample_cnt[2]), .Z(n6)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(151[8:38])
    defparam i1_2_lut_adj_65.init = 16'heeee;
    FD1S3AX r_uart_rx_falling_62 (.D(r_uart_rx_falling_N_875), .CK(clk_c), 
            .Q(nstate_1__N_801[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(90[9] 93[12])
    defparam r_uart_rx_falling_62.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i7 (.D(r_shift[8]), .SP(clk_c_enable_36), .CK(clk_c), 
            .Q(rx_data[7])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i7.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i6 (.D(r_shift[7]), .SP(clk_c_enable_36), .CK(clk_c), 
            .Q(rx_data[6])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i6.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_381__i1 (.D(n33[1]), .SP(clk_c_enable_224), .CD(n2597), 
            .CK(clk_c), .Q(r_sample_cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(172[37:56])
    defparam r_sample_cnt_381__i1.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i5 (.D(r_shift[6]), .SP(clk_c_enable_36), .CK(clk_c), 
            .Q(rx_data[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i5.GSR = "ENABLED";
    FD1S3AX busy_f_70 (.D(busy), .CK(clk_c), .Q(busy_f)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(191[8] 193[6])
    defparam busy_f_70.GSR = "ENABLED";
    FD1S3AX r_uart_rx_buf_61 (.D(rx_c), .CK(clk_c), .Q(r_uart_rx_buf)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(90[9] 93[12])
    defparam r_uart_rx_buf_61.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i4 (.D(r_shift[5]), .SP(clk_c_enable_36), .CK(clk_c), 
            .Q(rx_data[4])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i4.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i3 (.D(r_shift[4]), .SP(clk_c_enable_36), .CK(clk_c), 
            .Q(rx_data[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i3.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i2 (.D(r_shift[3]), .SP(clk_c_enable_36), .CK(clk_c), 
            .Q(rx_data[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i2.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i1 (.D(r_shift[2]), .SP(clk_c_enable_36), .CK(clk_c), 
            .Q(rx_data[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i1.GSR = "ENABLED";
    LUT4 i2_3_lut (.A(r_sample_cnt[1]), .B(r_sample_cnt[5]), .C(r_sample_cnt[0]), 
         .Z(n3874)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i2_3_lut.init = 16'h8080;
    FD1P3JX r_shift__0__i1 (.D(r_shift[2]), .SP(clk_c_enable_223), .PD(n2583), 
            .CK(clk_c), .Q(r_shift[1]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i1.GSR = "ENABLED";
    FD1P3JX r_shift__0__i2 (.D(r_shift[3]), .SP(clk_c_enable_223), .PD(n2583), 
            .CK(clk_c), .Q(r_shift[2]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i2.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_381__i2 (.D(n33[2]), .SP(clk_c_enable_224), .CD(n2597), 
            .CK(clk_c), .Q(r_sample_cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(172[37:56])
    defparam r_sample_cnt_381__i2.GSR = "ENABLED";
    FD1S3IX cstate_FSM_i2 (.D(n1384[1]), .CK(clk_c), .CD(nstate_1__N_799[0]), 
            .Q(n1384[2]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(111[9] 126[17])
    defparam cstate_FSM_i2.GSR = "ENABLED";
    FD1S3AX cstate_FSM_i1 (.D(n1838), .CK(clk_c), .Q(n1384[1]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(111[9] 126[17])
    defparam cstate_FSM_i1.GSR = "ENABLED";
    CCU2D r_sample_cnt_381_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(r_sample_cnt[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n3802), .S1(n33[0]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(172[37:56])
    defparam r_sample_cnt_381_add_4_1.INIT0 = 16'hF000;
    defparam r_sample_cnt_381_add_4_1.INIT1 = 16'h0555;
    defparam r_sample_cnt_381_add_4_1.INJECT1_0 = "NO";
    defparam r_sample_cnt_381_add_4_1.INJECT1_1 = "NO";
    CCU2D r_sample_cnt_381_add_4_3 (.A0(r_sample_cnt[1]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(r_sample_cnt[2]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n3802), .COUT(n3803), .S0(n33[1]), 
          .S1(n33[2]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(172[37:56])
    defparam r_sample_cnt_381_add_4_3.INIT0 = 16'hfaaa;
    defparam r_sample_cnt_381_add_4_3.INIT1 = 16'hfaaa;
    defparam r_sample_cnt_381_add_4_3.INJECT1_0 = "NO";
    defparam r_sample_cnt_381_add_4_3.INJECT1_1 = "NO";
    FD1P3IX r_shift_cnt_379__i3 (.D(n21[3]), .SP(clk_c_enable_66), .CD(n2583), 
            .CK(clk_c), .Q(r_shift_cnt[3]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(146[36:54])
    defparam r_shift_cnt_379__i3.GSR = "ENABLED";
    FD1P3IX r_shift_cnt_379__i1 (.D(n21[1]), .SP(clk_c_enable_66), .CD(n2583), 
            .CK(clk_c), .Q(r_shift_cnt[1]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(146[36:54])
    defparam r_shift_cnt_379__i1.GSR = "ENABLED";
    FD1P3IX r_shift_cnt_379__i2 (.D(n21[2]), .SP(clk_c_enable_66), .CD(n2583), 
            .CK(clk_c), .Q(r_shift_cnt[2]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(146[36:54])
    defparam r_shift_cnt_379__i2.GSR = "ENABLED";
    FD1S3JX cstate_FSM_i0 (.D(n1861), .CK(clk_c), .PD(n1384[2]), .Q(n1384[0]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(111[9] 126[17])
    defparam cstate_FSM_i0.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_381__i3 (.D(n33[3]), .SP(clk_c_enable_224), .CD(n2597), 
            .CK(clk_c), .Q(r_sample_cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(172[37:56])
    defparam r_sample_cnt_381__i3.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_381__i4 (.D(n33[4]), .SP(clk_c_enable_224), .CD(n2597), 
            .CK(clk_c), .Q(r_sample_cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(172[37:56])
    defparam r_sample_cnt_381__i4.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_381__i5 (.D(n33[5]), .SP(clk_c_enable_224), .CD(n2597), 
            .CK(clk_c), .Q(r_sample_cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(172[37:56])
    defparam r_sample_cnt_381__i5.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_381__i6 (.D(n33[6]), .SP(clk_c_enable_224), .CD(n2597), 
            .CK(clk_c), .Q(r_sample_cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(172[37:56])
    defparam r_sample_cnt_381__i6.GSR = "ENABLED";
    LUT4 i730_4_lut (.A(n1384[1]), .B(nstate_1__N_801[0]), .C(nstate_1__N_799[0]), 
         .D(n1384[0]), .Z(n1838)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(111[9] 126[17])
    defparam i730_4_lut.init = 16'heca0;
    FD1P3JX r_shift__0__i3 (.D(r_shift[4]), .SP(clk_c_enable_223), .PD(n2583), 
            .CK(clk_c), .Q(r_shift[3]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i3.GSR = "ENABLED";
    LUT4 i3198_2_lut_3_lut (.A(n1384[0]), .B(n1384[2]), .C(n1384[1]), 
         .Z(n2583)) /* synthesis lut_function=(!(A ((C)+!B)+!A (C))) */ ;
    defparam i3198_2_lut_3_lut.init = 16'h0d0d;
    LUT4 i311_3_lut_4_lut (.A(n1384[0]), .B(n1384[2]), .C(n1384[1]), .D(n13), 
         .Z(clk_c_enable_223)) /* synthesis lut_function=(!(A (B (C (D))+!B ((D)+!C))+!A (C (D)))) */ ;
    defparam i311_3_lut_4_lut.init = 16'h0dfd;
    LUT4 i1_2_lut_3_lut (.A(n1384[0]), .B(n1384[2]), .C(n1384[1]), .Z(clk_c_enable_66)) /* synthesis lut_function=((B+(C))+!A) */ ;
    defparam i1_2_lut_3_lut.init = 16'hfdfd;
    LUT4 busy_N_869_I_0_2_lut_rep_64 (.A(n1384[0]), .B(busy_f), .Z(n4634)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(186[21:37])
    defparam busy_N_869_I_0_2_lut_rep_64.init = 16'h8888;
    LUT4 i451_2_lut_3_lut_4_lut (.A(n1384[0]), .B(busy_f), .C(\cnt[1] ), 
         .D(\cnt[0] ), .Z(\cnt_2__N_963[1] )) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(186[21:37])
    defparam i451_2_lut_3_lut_4_lut.init = 16'h78f0;
    LUT4 n3874_bdd_3_lut (.A(n1384[0]), .B(n1384[2]), .C(nstate_1__N_801[0]), 
         .Z(n4602)) /* synthesis lut_function=(!(A (B+!(C))+!A (B))) */ ;
    defparam n3874_bdd_3_lut.init = 16'h3131;
    LUT4 i2_3_lut_4_lut (.A(n1384[0]), .B(busy_f), .C(cst), .D(n4635), 
         .Z(n28)) /* synthesis lut_function=(A (B+((D)+!C))+!A ((D)+!C)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(186[21:37])
    defparam i2_3_lut_4_lut.init = 16'hff8f;
    LUT4 i1_2_lut_3_lut_4_lut (.A(n1384[0]), .B(busy_f), .C(n4635), .D(n4616), 
         .Z(clk_c_enable_177)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(186[21:37])
    defparam i1_2_lut_3_lut_4_lut.init = 16'h8000;
    LUT4 i2648_3_lut_4_lut (.A(r_shift_cnt[1]), .B(n4623), .C(r_shift_cnt[2]), 
         .D(r_shift_cnt[3]), .Z(n21[3])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(146[36:54])
    defparam i2648_3_lut_4_lut.init = 16'h7f80;
    FD1P3JX r_shift__0__i4 (.D(r_shift[5]), .SP(clk_c_enable_223), .PD(n2583), 
            .CK(clk_c), .Q(r_shift[4]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i4.GSR = "ENABLED";
    FD1P3JX r_shift__0__i5 (.D(r_shift[6]), .SP(clk_c_enable_223), .PD(n2583), 
            .CK(clk_c), .Q(r_shift[5]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i5.GSR = "ENABLED";
    FD1P3JX r_shift__0__i6 (.D(r_shift[7]), .SP(clk_c_enable_223), .PD(n2583), 
            .CK(clk_c), .Q(r_shift[6]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i6.GSR = "ENABLED";
    FD1P3JX r_shift__0__i7 (.D(r_shift[8]), .SP(clk_c_enable_223), .PD(n2583), 
            .CK(clk_c), .Q(r_shift[7]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i7.GSR = "ENABLED";
    FD1P3JX r_shift__0__i8 (.D(r_shift[9]), .SP(clk_c_enable_223), .PD(n2583), 
            .CK(clk_c), .Q(r_shift[8]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i8.GSR = "ENABLED";
    FD1P3JX r_shift__0__i9 (.D(rx_c), .SP(clk_c_enable_223), .PD(n2583), 
            .CK(clk_c), .Q(r_shift[9]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i9.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_381__i0 (.D(n33[0]), .SP(clk_c_enable_224), .CD(n2597), 
            .CK(clk_c), .Q(r_sample_cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(172[37:56])
    defparam r_sample_cnt_381__i0.GSR = "ENABLED";
    LUT4 i1_2_lut_rep_55_3_lut (.A(n1384[0]), .B(busy_f), .C(\cnt[1] ), 
         .Z(n4625)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(186[21:37])
    defparam i1_2_lut_rep_55_3_lut.init = 16'h0808;
    LUT4 i443_2_lut_3_lut (.A(n1384[0]), .B(busy_f), .C(\cnt[0] ), .Z(\cnt_2__N_963[0] )) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(186[21:37])
    defparam i443_2_lut_3_lut.init = 16'h7878;
    LUT4 i151_2_lut (.A(n1384[2]), .B(n1384[1]), .Z(clk_c_enable_36)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(156[18] 180[16])
    defparam i151_2_lut.init = 16'h2222;
    LUT4 n4600_bdd_4_lut (.A(n4600), .B(n3874), .C(n4602), .D(n1384[1]), 
         .Z(n2597)) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A !((D)+!C)) */ ;
    defparam n4600_bdd_4_lut.init = 16'h88f0;
    LUT4 r_uart_rx_falling_I_13_2_lut (.A(rx_c), .B(r_uart_rx_buf), .Z(r_uart_rx_falling_N_875)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(92[25:46])
    defparam r_uart_rx_falling_I_13_2_lut.init = 16'h4444;
    LUT4 i3216_4_lut (.A(n9), .B(n4310), .C(n1384[2]), .D(r_sample_cnt[5]), 
         .Z(clk_c_enable_224)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;
    defparam i3216_4_lut.init = 16'hfdff;
    LUT4 i3_4_lut (.A(r_sample_cnt[6]), .B(n1384[0]), .C(r_sample_cnt[3]), 
         .D(r_sample_cnt[4]), .Z(n9)) /* synthesis lut_function=(A (B (C+(D)))) */ ;
    defparam i3_4_lut.init = 16'h8880;
    LUT4 i3134_2_lut (.A(nstate_1__N_801[0]), .B(n1384[1]), .Z(n4310)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i3134_2_lut.init = 16'heeee;
    LUT4 busy_I_0_1_lut (.A(n1384[0]), .Z(busy)) /* synthesis lut_function=(!(A)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(76[19:48])
    defparam busy_I_0_1_lut.init = 16'h5555;
    LUT4 i2628_2_lut_rep_53 (.A(n13), .B(r_shift_cnt[0]), .Z(n4623)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(146[36:54])
    defparam i2628_2_lut_rep_53.init = 16'h4444;
    LUT4 i2634_2_lut_3_lut (.A(n13), .B(r_shift_cnt[0]), .C(r_shift_cnt[1]), 
         .Z(n21[1])) /* synthesis lut_function=(A (C)+!A !(B (C)+!B !(C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(146[36:54])
    defparam i2634_2_lut_3_lut.init = 16'hb4b4;
    LUT4 i2641_2_lut_3_lut_4_lut (.A(n13), .B(r_shift_cnt[0]), .C(r_shift_cnt[2]), 
         .D(r_shift_cnt[1]), .Z(n21[2])) /* synthesis lut_function=(A (C)+!A !(B (C (D)+!C !(D))+!B !(C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(146[36:54])
    defparam i2641_2_lut_3_lut_4_lut.init = 16'hb4f0;
    CCU2D r_sample_cnt_381_add_4_7 (.A0(r_sample_cnt[5]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(r_sample_cnt[6]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n3804), .S0(n33[5]), .S1(n33[6]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(172[37:56])
    defparam r_sample_cnt_381_add_4_7.INIT0 = 16'hfaaa;
    defparam r_sample_cnt_381_add_4_7.INIT1 = 16'hfaaa;
    defparam r_sample_cnt_381_add_4_7.INJECT1_0 = "NO";
    defparam r_sample_cnt_381_add_4_7.INJECT1_1 = "NO";
    CCU2D r_sample_cnt_381_add_4_5 (.A0(r_sample_cnt[3]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(r_sample_cnt[4]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n3803), .COUT(n3804), .S0(n33[3]), 
          .S1(n33[4]));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(172[37:56])
    defparam r_sample_cnt_381_add_4_5.INIT0 = 16'hfaaa;
    defparam r_sample_cnt_381_add_4_5.INIT1 = 16'hfaaa;
    defparam r_sample_cnt_381_add_4_5.INJECT1_0 = "NO";
    defparam r_sample_cnt_381_add_4_5.INJECT1_1 = "NO";
    
endmodule
//
// Verilog Description of module Debug_core_DecodeUart
//

module Debug_core_DecodeUart (valid_o, clk_c, n4932, cnt, n4634, cmd, 
            rx_data, cmd_data, cst, rst_n, n4632, n4619, clk_c_enable_225, 
            clk_c_enable_147, clk_c_enable_296, n4625, n4627, n4332, 
            clk_c_enable_265, ope, clk_c_enable_216, \cnt_2__N_963[0] , 
            n4616, \cnt_2__N_963[1] , clk_c_enable_177, n4635, n28) /* synthesis syn_module_defined=1 */ ;
    output valid_o;
    input clk_c;
    input n4932;
    output [2:0]cnt;
    input n4634;
    output [7:0]cmd;
    input [7:0]rx_data;
    output [31:0]cmd_data;
    output cst;
    input rst_n;
    output n4632;
    input n4619;
    output clk_c_enable_225;
    output clk_c_enable_147;
    output clk_c_enable_296;
    input n4625;
    input n4627;
    input n4332;
    output clk_c_enable_265;
    input ope;
    output clk_c_enable_216;
    input \cnt_2__N_963[0] ;
    output n4616;
    input \cnt_2__N_963[1] ;
    input clk_c_enable_177;
    output n4635;
    input n28;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(3[8:11])
    
    wire clk_c_enable_19, n2593;
    wire [2:0]cnt_c;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(372[11:14])
    wire [2:0]cnt_2__N_963;
    
    wire clk_c_enable_154, clk_c_enable_161, n4622, n8, clk_c_enable_169, 
        n4633, clk_c_enable_185, n4199;
    wire [31:0]nst_N_973;
    
    wire n4216, n6, n12, n12_adj_1042, n8_adj_1043, n2379;
    
    FD1P3IX valid_o_72 (.D(n4932), .SP(clk_c_enable_19), .CD(n2593), .CK(clk_c), 
            .Q(valid_o));   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam valid_o_72.GSR = "ENABLED";
    LUT4 i458_3_lut_4_lut (.A(cnt[0]), .B(n4634), .C(cnt[1]), .D(cnt_c[2]), 
         .Z(cnt_2__N_963[2])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;
    defparam i458_3_lut_4_lut.init = 16'h7f80;
    FD1P3AX cmd_i0 (.D(rx_data[0]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(cmd[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam cmd_i0.GSR = "ENABLED";
    FD1P3AX data_i0 (.D(rx_data[0]), .SP(clk_c_enable_161), .CK(clk_c), 
            .Q(cmd_data[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i0.GSR = "ENABLED";
    FD1S3AX cst_70 (.D(n4622), .CK(clk_c), .Q(cst)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(379[9:21])
    defparam cst_70.GSR = "ENABLED";
    LUT4 rst_n_I_0_1_lut_rep_62 (.A(rst_n), .Z(n4632)) /* synthesis lut_function=(!(A)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(48[8:14])
    defparam rst_n_I_0_1_lut_rep_62.init = 16'h5555;
    LUT4 i1_2_lut_4_lut_4_lut (.A(rst_n), .B(n4619), .C(cmd[1]), .D(cmd[0]), 
         .Z(clk_c_enable_225)) /* synthesis lut_function=(!(A (((D)+!C)+!B))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(48[8:14])
    defparam i1_2_lut_4_lut_4_lut.init = 16'h55d5;
    LUT4 i387_3_lut_4_lut_4_lut (.A(rst_n), .B(cmd[1]), .C(n4619), .D(cmd[0]), 
         .Z(clk_c_enable_147)) /* synthesis lut_function=((B (C (D)))+!A) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(48[8:14])
    defparam i387_3_lut_4_lut_4_lut.init = 16'hd555;
    LUT4 i385_2_lut_2_lut (.A(rst_n), .B(valid_o), .Z(clk_c_enable_296)) /* synthesis lut_function=((B)+!A) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(48[8:14])
    defparam i385_2_lut_2_lut.init = 16'hdddd;
    LUT4 i3_4_lut (.A(cnt[0]), .B(n8), .C(cnt_c[2]), .D(n4625), .Z(clk_c_enable_169)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;
    defparam i3_4_lut.init = 16'h4000;
    LUT4 i388_4_lut_4_lut (.A(rst_n), .B(n4627), .C(cmd[2]), .D(n4332), 
         .Z(clk_c_enable_265)) /* synthesis lut_function=(!(A (((D)+!C)+!B))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(48[8:14])
    defparam i388_4_lut_4_lut.init = 16'h55d5;
    LUT4 i389_2_lut_2_lut (.A(rst_n), .B(ope), .Z(clk_c_enable_216)) /* synthesis lut_function=((B)+!A) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(48[8:14])
    defparam i389_2_lut_2_lut.init = 16'hdddd;
    FD1S3IX cnt_i0 (.D(\cnt_2__N_963[0] ), .CK(clk_c), .CD(n2593), .Q(cnt[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam cnt_i0.GSR = "ENABLED";
    LUT4 i1_2_lut_rep_63 (.A(cnt[1]), .B(cnt[0]), .Z(n4633)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(409[24:35])
    defparam i1_2_lut_rep_63.init = 16'h2222;
    LUT4 i1_2_lut_3_lut_4_lut (.A(cnt[1]), .B(cnt[0]), .C(n4616), .D(n4634), 
         .Z(clk_c_enable_185)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(409[24:35])
    defparam i1_2_lut_3_lut_4_lut.init = 16'h2000;
    FD1S3IX cnt_i1 (.D(\cnt_2__N_963[1] ), .CK(clk_c), .CD(n2593), .Q(cnt[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam cnt_i1.GSR = "ENABLED";
    FD1S3IX cnt_i2 (.D(cnt_2__N_963[2]), .CK(clk_c), .CD(n2593), .Q(cnt_c[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam cnt_i2.GSR = "ENABLED";
    FD1P3AX cmd_i1 (.D(rx_data[1]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(cmd[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam cmd_i1.GSR = "ENABLED";
    FD1P3AX cmd_i2 (.D(rx_data[2]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(cmd[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam cmd_i2.GSR = "ENABLED";
    FD1P3AX cmd_i3 (.D(rx_data[3]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(cmd[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam cmd_i3.GSR = "ENABLED";
    FD1P3AX cmd_i4 (.D(rx_data[4]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(cmd[4])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam cmd_i4.GSR = "ENABLED";
    FD1P3AX cmd_i5 (.D(rx_data[5]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(cmd[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam cmd_i5.GSR = "ENABLED";
    FD1P3AX cmd_i6 (.D(rx_data[6]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(cmd[6])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam cmd_i6.GSR = "ENABLED";
    FD1P3AX cmd_i7 (.D(rx_data[7]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(cmd[7])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam cmd_i7.GSR = "ENABLED";
    FD1P3AX data_i1 (.D(rx_data[1]), .SP(clk_c_enable_161), .CK(clk_c), 
            .Q(cmd_data[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i1.GSR = "ENABLED";
    FD1P3AX data_i2 (.D(rx_data[2]), .SP(clk_c_enable_161), .CK(clk_c), 
            .Q(cmd_data[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i2.GSR = "ENABLED";
    FD1P3AX data_i3 (.D(rx_data[3]), .SP(clk_c_enable_161), .CK(clk_c), 
            .Q(cmd_data[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i3.GSR = "ENABLED";
    FD1P3AX data_i4 (.D(rx_data[4]), .SP(clk_c_enable_161), .CK(clk_c), 
            .Q(cmd_data[4])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i4.GSR = "ENABLED";
    FD1P3AX data_i5 (.D(rx_data[5]), .SP(clk_c_enable_161), .CK(clk_c), 
            .Q(cmd_data[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i5.GSR = "ENABLED";
    FD1P3AX data_i6 (.D(rx_data[6]), .SP(clk_c_enable_161), .CK(clk_c), 
            .Q(cmd_data[6])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i6.GSR = "ENABLED";
    FD1P3AX data_i7 (.D(rx_data[7]), .SP(clk_c_enable_161), .CK(clk_c), 
            .Q(cmd_data[7])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i7.GSR = "ENABLED";
    FD1P3AX data_i8 (.D(rx_data[0]), .SP(clk_c_enable_169), .CK(clk_c), 
            .Q(cmd_data[8])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i8.GSR = "ENABLED";
    FD1P3AX data_i9 (.D(rx_data[1]), .SP(clk_c_enable_169), .CK(clk_c), 
            .Q(cmd_data[9])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i9.GSR = "ENABLED";
    FD1P3AX data_i10 (.D(rx_data[2]), .SP(clk_c_enable_169), .CK(clk_c), 
            .Q(cmd_data[10])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i10.GSR = "ENABLED";
    FD1P3AX data_i11 (.D(rx_data[3]), .SP(clk_c_enable_169), .CK(clk_c), 
            .Q(cmd_data[11])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i11.GSR = "ENABLED";
    FD1P3AX data_i12 (.D(rx_data[4]), .SP(clk_c_enable_169), .CK(clk_c), 
            .Q(cmd_data[12])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i12.GSR = "ENABLED";
    FD1P3AX data_i13 (.D(rx_data[5]), .SP(clk_c_enable_169), .CK(clk_c), 
            .Q(cmd_data[13])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i13.GSR = "ENABLED";
    FD1P3AX data_i14 (.D(rx_data[6]), .SP(clk_c_enable_169), .CK(clk_c), 
            .Q(cmd_data[14])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i14.GSR = "ENABLED";
    FD1P3AX data_i15 (.D(rx_data[7]), .SP(clk_c_enable_169), .CK(clk_c), 
            .Q(cmd_data[15])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i15.GSR = "ENABLED";
    FD1P3AX data_i16 (.D(rx_data[0]), .SP(clk_c_enable_177), .CK(clk_c), 
            .Q(cmd_data[16])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i16.GSR = "ENABLED";
    FD1P3AX data_i17 (.D(rx_data[1]), .SP(clk_c_enable_177), .CK(clk_c), 
            .Q(cmd_data[17])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i17.GSR = "ENABLED";
    FD1P3AX data_i18 (.D(rx_data[2]), .SP(clk_c_enable_177), .CK(clk_c), 
            .Q(cmd_data[18])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i18.GSR = "ENABLED";
    FD1P3AX data_i19 (.D(rx_data[3]), .SP(clk_c_enable_177), .CK(clk_c), 
            .Q(cmd_data[19])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i19.GSR = "ENABLED";
    FD1P3AX data_i20 (.D(rx_data[4]), .SP(clk_c_enable_177), .CK(clk_c), 
            .Q(cmd_data[20])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i20.GSR = "ENABLED";
    FD1P3AX data_i21 (.D(rx_data[5]), .SP(clk_c_enable_177), .CK(clk_c), 
            .Q(cmd_data[21])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i21.GSR = "ENABLED";
    FD1P3AX data_i22 (.D(rx_data[6]), .SP(clk_c_enable_177), .CK(clk_c), 
            .Q(cmd_data[22])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i22.GSR = "ENABLED";
    FD1P3AX data_i23 (.D(rx_data[7]), .SP(clk_c_enable_177), .CK(clk_c), 
            .Q(cmd_data[23])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i23.GSR = "ENABLED";
    FD1P3AX data_i24 (.D(rx_data[0]), .SP(clk_c_enable_185), .CK(clk_c), 
            .Q(cmd_data[24])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i24.GSR = "ENABLED";
    FD1P3AX data_i25 (.D(rx_data[1]), .SP(clk_c_enable_185), .CK(clk_c), 
            .Q(cmd_data[25])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i25.GSR = "ENABLED";
    FD1P3AX data_i26 (.D(rx_data[2]), .SP(clk_c_enable_185), .CK(clk_c), 
            .Q(cmd_data[26])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i26.GSR = "ENABLED";
    FD1P3AX data_i27 (.D(rx_data[3]), .SP(clk_c_enable_185), .CK(clk_c), 
            .Q(cmd_data[27])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i27.GSR = "ENABLED";
    FD1P3AX data_i28 (.D(rx_data[4]), .SP(clk_c_enable_185), .CK(clk_c), 
            .Q(cmd_data[28])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i28.GSR = "ENABLED";
    FD1P3AX data_i29 (.D(rx_data[5]), .SP(clk_c_enable_185), .CK(clk_c), 
            .Q(cmd_data[29])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i29.GSR = "ENABLED";
    FD1P3AX data_i30 (.D(rx_data[6]), .SP(clk_c_enable_185), .CK(clk_c), 
            .Q(cmd_data[30])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i30.GSR = "ENABLED";
    FD1P3AX data_i31 (.D(rx_data[7]), .SP(clk_c_enable_185), .CK(clk_c), 
            .Q(cmd_data[31])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(399[10] 418[8])
    defparam data_i31.GSR = "ENABLED";
    LUT4 i1_3_lut_rep_46 (.A(cnt_c[2]), .B(cst), .C(n4199), .Z(n4616)) /* synthesis lut_function=(!(A+!(B+(C)))) */ ;
    defparam i1_3_lut_rep_46.init = 16'h5454;
    LUT4 i2206_2_lut_rep_65 (.A(cnt[1]), .B(cnt[0]), .Z(n4635)) /* synthesis lut_function=(A (B)) */ ;
    defparam i2206_2_lut_rep_65.init = 16'h8888;
    LUT4 i19_3_lut_4_lut (.A(cnt[1]), .B(cnt[0]), .C(cst), .D(n4199), 
         .Z(n8)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+(D)))+!A !(C+(D)))) */ ;
    defparam i19_3_lut_4_lut.init = 16'h7f70;
    LUT4 i2360_2_lut_3_lut (.A(cnt[1]), .B(cnt[0]), .C(cnt_c[2]), .Z(nst_N_973[0])) /* synthesis lut_function=(!(A (B (C)))) */ ;
    defparam i2360_2_lut_3_lut.init = 16'h7f7f;
    LUT4 i4_4_lut (.A(cnt_c[2]), .B(n4633), .C(n4216), .D(n6), .Z(clk_c_enable_19)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(409[24:35])
    defparam i4_4_lut.init = 16'h8000;
    LUT4 i6_4_lut (.A(n28), .B(n12), .C(rx_data[3]), .D(rx_data[7]), 
         .Z(n4216)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(409[24:35])
    defparam i6_4_lut.init = 16'h0008;
    LUT4 i1_2_lut (.A(rx_data[4]), .B(rx_data[2]), .Z(n6)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(409[24:35])
    defparam i1_2_lut.init = 16'h8888;
    LUT4 i5_4_lut (.A(rx_data[5]), .B(rx_data[1]), .C(rx_data[0]), .D(rx_data[6]), 
         .Z(n12)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/debug_core.v(409[24:35])
    defparam i5_4_lut.init = 16'h1000;
    LUT4 i6_4_lut_adj_61 (.A(rx_data[4]), .B(n12_adj_1042), .C(n8_adj_1043), 
         .D(rx_data[2]), .Z(n4199)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
    defparam i6_4_lut_adj_61.init = 16'h0040;
    LUT4 i5_4_lut_adj_62 (.A(rx_data[7]), .B(rx_data[6]), .C(rx_data[3]), 
         .D(rx_data[0]), .Z(n12_adj_1042)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;
    defparam i5_4_lut_adj_62.init = 16'h0020;
    LUT4 i1_2_lut_adj_63 (.A(rx_data[5]), .B(rx_data[1]), .Z(n8_adj_1043)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_63.init = 16'h8888;
    LUT4 i3_4_lut_adj_64 (.A(cnt[0]), .B(cnt_c[2]), .C(n2379), .D(cnt[1]), 
         .Z(clk_c_enable_161)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;
    defparam i3_4_lut_adj_64.init = 16'h0080;
    LUT4 rx_valid_bdd_4_lut_rep_52 (.A(n4634), .B(n4199), .C(nst_N_973[0]), 
         .D(cst), .Z(n4622)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C (D))) */ ;
    defparam rx_valid_bdd_4_lut_rep_52.init = 16'hf088;
    LUT4 i1_2_lut_4_lut (.A(n4634), .B(n4199), .C(nst_N_973[0]), .D(cst), 
         .Z(n2379)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;
    defparam i1_2_lut_4_lut.init = 16'ha088;
    LUT4 i1479_1_lut_4_lut (.A(n4634), .B(n4199), .C(nst_N_973[0]), .D(cst), 
         .Z(n2593)) /* synthesis lut_function=(!(A (B (C+!(D))+!B (C (D)))+!A (C (D)))) */ ;
    defparam i1479_1_lut_4_lut.init = 16'h0f77;
    LUT4 i2_3_lut_4_lut (.A(n4634), .B(cnt[1]), .C(cnt[0]), .D(n4616), 
         .Z(clk_c_enable_154)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;
    defparam i2_3_lut_4_lut.init = 16'h2000;
    
endmodule
//
// Verilog Description of module LedStatus
//

module LedStatus (led_c, clk_c, led_status, GND_net) /* synthesis syn_module_defined=1 */ ;
    output led_c;
    input clk_c;
    input [2:0]led_status;
    input GND_net;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/top.v(3[8:11])
    
    wire clk_c_enable_11, led_N_484;
    wire [31:0]cnt;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    
    wire clk_c_enable_87, n2601;
    wire [31:0]n133;
    
    wire n4288, n3611, n4559, n4617, n2476, n4284, n4281, n4304, 
        n3915, n4290, n4299, n4254, n4610, n4358, n4, n4302, 
        n4639, n4561, n4560, n48, n4344, n4227, n3621, n52, 
        n25, n31, n4318, n4340, n4_adj_1037, n4558, n2452, n8, 
        n3917, n4_adj_1038, n30, n4245, n3625, n4258, n4228, n4357, 
        n4231, n4608, n208, n4615, n9, n4233, n11, n4400, n3113, 
        n12, n201, n4636, n14, n12_adj_1039, n4638, n4275, n3593, 
        n262, n5, n212, n4397, n226, n4243, n288, n215, n3436, 
        n4226, n4253, n4246, n27, n20, n3841, n3914, n4252, 
        n3840, n3877, n4255, n3839, n4_adj_1040, n3838, n3916, 
        n3837, n3836, n3835, n5_adj_1041, n6, n4260, n3834, n3833, 
        n3832, n3831, n3830, n3829, n3828, n3827, n3826;
    
    FD1P3AY led_36 (.D(led_N_484), .SP(clk_c_enable_11), .CK(clk_c), .Q(led_c)) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=28, LSE_RLINE=33 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(52[10] 78[8])
    defparam led_36.GSR = "ENABLED";
    FD1P3IX cnt_378__i5 (.D(n133[5]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i5.GSR = "ENABLED";
    FD1P3IX cnt_378__i4 (.D(n133[4]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i4.GSR = "ENABLED";
    FD1P3IX cnt_378__i3 (.D(n133[3]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i3.GSR = "ENABLED";
    FD1P3IX cnt_378__i2 (.D(n133[2]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i2.GSR = "ENABLED";
    FD1P3IX cnt_378__i1 (.D(n133[1]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i1.GSR = "ENABLED";
    FD1P3IX cnt_378__i0 (.D(n133[0]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i0.GSR = "ENABLED";
    LUT4 n4288_bdd_3_lut (.A(n4288), .B(n3611), .C(led_status[0]), .Z(n4559)) /* synthesis lut_function=(A (B+(C))+!A !((C)+!B)) */ ;
    defparam n4288_bdd_3_lut.init = 16'hacac;
    LUT4 i1_2_lut_3_lut_4_lut (.A(cnt[23]), .B(n4617), .C(cnt[21]), .D(cnt[22]), 
         .Z(n2476)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i1_2_lut_3_lut_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut_3_lut (.A(cnt[17]), .B(cnt[16]), .C(cnt[18]), .Z(n4284)) /* synthesis lut_function=(A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam i1_2_lut_3_lut.init = 16'h8080;
    LUT4 i1_2_lut_3_lut_adj_19 (.A(cnt[17]), .B(cnt[16]), .C(cnt[15]), 
         .Z(n4281)) /* synthesis lut_function=(A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam i1_2_lut_3_lut_adj_19.init = 16'h8080;
    LUT4 i2_4_lut (.A(cnt[13]), .B(cnt[14]), .C(n4304), .D(cnt[15]), 
         .Z(n3915)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B+(D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i2_4_lut.init = 16'hffec;
    LUT4 i1_2_lut_3_lut_adj_20 (.A(cnt[13]), .B(cnt[14]), .C(cnt[12]), 
         .Z(n4290)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i1_2_lut_3_lut_adj_20.init = 16'hfefe;
    LUT4 i1_2_lut_3_lut_adj_21 (.A(cnt[13]), .B(cnt[14]), .C(cnt[15]), 
         .Z(n4299)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i1_2_lut_3_lut_adj_21.init = 16'hfefe;
    LUT4 i3187_1_lut_4_lut (.A(n4254), .B(n4610), .C(cnt[22]), .D(cnt[21]), 
         .Z(n4358)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C (D))))) */ ;
    defparam i3187_1_lut_4_lut.init = 16'h0313;
    FD1P3IX cnt_378__i27 (.D(n133[27]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[27])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i27.GSR = "ENABLED";
    FD1P3IX cnt_378__i28 (.D(n133[28]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[28])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i28.GSR = "ENABLED";
    FD1P3IX cnt_378__i29 (.D(n133[29]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[29])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i29.GSR = "ENABLED";
    FD1P3IX cnt_378__i30 (.D(n133[30]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[30])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i30.GSR = "ENABLED";
    FD1P3IX cnt_378__i31 (.D(n133[31]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[31])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i31.GSR = "ENABLED";
    FD1P3IX cnt_378__i26 (.D(n133[26]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[26])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i26.GSR = "ENABLED";
    FD1P3IX cnt_378__i24 (.D(n133[24]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[24])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i24.GSR = "ENABLED";
    FD1P3IX cnt_378__i23 (.D(n133[23]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[23])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i23.GSR = "ENABLED";
    FD1P3IX cnt_378__i25 (.D(n133[25]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[25])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i25.GSR = "ENABLED";
    FD1P3IX cnt_378__i22 (.D(n133[22]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[22])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i22.GSR = "ENABLED";
    FD1P3IX cnt_378__i21 (.D(n133[21]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[21])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i21.GSR = "ENABLED";
    FD1P3IX cnt_378__i19 (.D(n133[19]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[19])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i19.GSR = "ENABLED";
    FD1P3IX cnt_378__i18 (.D(n133[18]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[18])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i18.GSR = "ENABLED";
    FD1P3IX cnt_378__i20 (.D(n133[20]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[20])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i20.GSR = "ENABLED";
    FD1P3IX cnt_378__i17 (.D(n133[17]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[17])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i17.GSR = "ENABLED";
    FD1P3IX cnt_378__i16 (.D(n133[16]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[16])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i16.GSR = "ENABLED";
    FD1P3IX cnt_378__i15 (.D(n133[15]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[15])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i15.GSR = "ENABLED";
    FD1P3IX cnt_378__i14 (.D(n133[14]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[14])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i14.GSR = "ENABLED";
    FD1P3IX cnt_378__i13 (.D(n133[13]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[13])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i13.GSR = "ENABLED";
    FD1P3IX cnt_378__i11 (.D(n133[11]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[11])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i11.GSR = "ENABLED";
    FD1P3IX cnt_378__i10 (.D(n133[10]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i10.GSR = "ENABLED";
    FD1P3IX cnt_378__i12 (.D(n133[12]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[12])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i12.GSR = "ENABLED";
    FD1P3IX cnt_378__i9 (.D(n133[9]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i9.GSR = "ENABLED";
    FD1P3IX cnt_378__i6 (.D(n133[6]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i6.GSR = "ENABLED";
    FD1P3IX cnt_378__i7 (.D(n133[7]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i7.GSR = "ENABLED";
    FD1P3IX cnt_378__i8 (.D(n133[8]), .SP(clk_c_enable_87), .CD(n2601), 
            .CK(clk_c), .Q(cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378__i8.GSR = "ENABLED";
    LUT4 i1_4_lut (.A(n4), .B(n4302), .C(cnt[6]), .D(n4639), .Z(n4304)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i1_4_lut.init = 16'heccc;
    LUT4 n4561_bdd_3_lut (.A(n4561), .B(n4560), .C(led_status[2]), .Z(led_N_484)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n4561_bdd_3_lut.init = 16'hcaca;
    LUT4 i3203_4_lut (.A(led_status[2]), .B(n48), .C(led_status[1]), .D(n4344), 
         .Z(n2601)) /* synthesis lut_function=(!(A (B)+!A (B+!(C (D))))) */ ;
    defparam i3203_4_lut.init = 16'h3222;
    LUT4 i2508_4_lut (.A(n4227), .B(n4617), .C(cnt[23]), .D(cnt[22]), 
         .Z(n3621)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2508_4_lut.init = 16'hfcec;
    LUT4 i52_4_lut (.A(n52), .B(n25), .C(led_status[1]), .D(n31), .Z(n48)) /* synthesis lut_function=(A (B+((D)+!C))+!A (B (C)+!B (C (D)))) */ ;
    defparam i52_4_lut.init = 16'hfaca;
    LUT4 i3168_4_lut (.A(n4318), .B(n4340), .C(cnt[29]), .D(cnt[27]), 
         .Z(n4344)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i3168_4_lut.init = 16'hfffe;
    LUT4 n4288_bdd_4_lut_3249 (.A(n2476), .B(n4_adj_1037), .C(cnt[20]), 
         .D(cnt[19]), .Z(n4558)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam n4288_bdd_4_lut_3249.init = 16'hfefa;
    LUT4 i1_4_lut_adj_22 (.A(led_status[0]), .B(cnt[24]), .C(n2452), .D(n8), 
         .Z(n25)) /* synthesis lut_function=(!((B (C+(D))+!B (C))+!A)) */ ;
    defparam i1_4_lut_adj_22.init = 16'h020a;
    LUT4 i1_4_lut_adj_23 (.A(n2476), .B(cnt[18]), .C(n3917), .D(cnt[17]), 
         .Z(n4_adj_1038)) /* synthesis lut_function=(A (B+(C+!(D)))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut_adj_23.init = 16'hfcee;
    LUT4 i3_4_lut (.A(cnt[15]), .B(cnt[16]), .C(n2476), .D(n30), .Z(n3917)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i3_4_lut.init = 16'hfffe;
    LUT4 i2512_4_lut (.A(n4245), .B(n2452), .C(cnt[24]), .D(cnt[23]), 
         .Z(n3625)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2512_4_lut.init = 16'hfcec;
    LUT4 i1_4_lut_adj_24 (.A(cnt[14]), .B(cnt[13]), .C(cnt[12]), .D(n4258), 
         .Z(n30)) /* synthesis lut_function=(A (B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i1_4_lut_adj_24.init = 16'haaa8;
    LUT4 i3186_1_lut_4_lut (.A(n4228), .B(n4617), .C(cnt[23]), .D(cnt[22]), 
         .Z(n4357)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C (D))))) */ ;
    defparam i3186_1_lut_4_lut.init = 16'h0313;
    LUT4 i1_4_lut_adj_25 (.A(n4231), .B(n4608), .C(cnt[21]), .D(cnt[20]), 
         .Z(n4288)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(70[24:52])
    defparam i1_4_lut_adj_25.init = 16'hfcec;
    LUT4 i3_4_lut_adj_26 (.A(n208), .B(n4615), .C(cnt[11]), .D(cnt[10]), 
         .Z(n4258)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i3_4_lut_adj_26.init = 16'h8000;
    LUT4 i2_4_lut_adj_27 (.A(cnt[19]), .B(cnt[20]), .C(cnt[18]), .D(n9), 
         .Z(n4233)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i2_4_lut_adj_27.init = 16'h8000;
    LUT4 i2_4_lut_adj_28 (.A(cnt[14]), .B(cnt[17]), .C(n11), .D(n4400), 
         .Z(n9)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B+(D))) */ ;
    defparam i2_4_lut_adj_28.init = 16'hffec;
    PFUMX i54 (.BLUT(n4357), .ALUT(n4358), .C0(led_status[0]), .Z(n52));
    LUT4 i1_2_lut_rep_45 (.A(cnt[7]), .B(n3113), .Z(n4615)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam i1_2_lut_rep_45.init = 16'heeee;
    LUT4 i6_4_lut (.A(cnt[4]), .B(n12), .C(cnt[1]), .D(cnt[3]), .Z(n3113)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam i6_4_lut.init = 16'h8000;
    LUT4 i5_4_lut (.A(cnt[0]), .B(cnt[2]), .C(cnt[5]), .D(cnt[6]), .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam i5_4_lut.init = 16'h8000;
    LUT4 i1_2_lut_3_lut_adj_29 (.A(cnt[7]), .B(n3113), .C(cnt[8]), .Z(n201)) /* synthesis lut_function=(A (C)+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam i1_2_lut_3_lut_adj_29.init = 16'he0e0;
    LUT4 i1_2_lut_rep_66 (.A(cnt[10]), .B(cnt[12]), .Z(n4636)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i1_2_lut_rep_66.init = 16'heeee;
    LUT4 i1_2_lut_rep_47 (.A(cnt[24]), .B(n2452), .Z(n4617)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut_rep_47.init = 16'heeee;
    LUT4 i27_4_lut_4_lut (.A(cnt[10]), .B(cnt[12]), .C(cnt[11]), .D(cnt[9]), 
         .Z(n14)) /* synthesis lut_function=(!(A (B (C (D))+!B ((D)+!C))+!A ((C (D))+!B))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i27_4_lut_4_lut.init = 16'h0cec;
    LUT4 i6_4_lut_adj_30 (.A(cnt[28]), .B(n12_adj_1039), .C(cnt[25]), 
         .D(cnt[27]), .Z(n2452)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i6_4_lut_adj_30.init = 16'hfffe;
    LUT4 i5_4_lut_adj_31 (.A(cnt[29]), .B(cnt[30]), .C(cnt[26]), .D(cnt[31]), 
         .Z(n12_adj_1039)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i5_4_lut_adj_31.init = 16'hfffe;
    LUT4 i1_2_lut_rep_68 (.A(cnt[19]), .B(cnt[18]), .Z(n4638)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_rep_68.init = 16'h8888;
    LUT4 i1_2_lut_3_lut_adj_32 (.A(cnt[19]), .B(cnt[18]), .C(cnt[17]), 
         .Z(n4275)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i1_2_lut_3_lut_adj_32.init = 16'h8080;
    LUT4 i1_2_lut_rep_69 (.A(cnt[8]), .B(cnt[7]), .Z(n4639)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam i1_2_lut_rep_69.init = 16'h8888;
    LUT4 i1_2_lut_rep_40_3_lut (.A(cnt[24]), .B(n2452), .C(cnt[23]), .Z(n4610)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i1_2_lut_rep_40_3_lut.init = 16'hfefe;
    LUT4 i1_2_lut_rep_38_3_lut_4_lut (.A(cnt[24]), .B(n2452), .C(cnt[22]), 
         .D(cnt[23]), .Z(n4608)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i1_2_lut_rep_38_3_lut_4_lut.init = 16'hfffe;
    LUT4 i1_3_lut (.A(led_status[2]), .B(led_status[0]), .C(n3593), .Z(n31)) /* synthesis lut_function=(A (B+!(C))) */ ;
    defparam i1_3_lut.init = 16'h8a8a;
    LUT4 i2_3_lut_4_lut (.A(cnt[8]), .B(cnt[7]), .C(cnt[13]), .D(n3113), 
         .Z(n262)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam i2_3_lut_4_lut.init = 16'h8000;
    LUT4 i1_4_lut_adj_33 (.A(cnt[23]), .B(n5), .C(cnt[21]), .D(cnt[22]), 
         .Z(n8)) /* synthesis lut_function=(A+(B (C (D)))) */ ;
    defparam i1_4_lut_adj_33.init = 16'heaaa;
    LUT4 i1_4_lut_adj_34 (.A(n212), .B(cnt[20]), .C(n4275), .D(n4397), 
         .Z(n5)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut_adj_34.init = 16'hfcec;
    LUT4 i1_4_lut_adj_35 (.A(n226), .B(n4243), .C(cnt[20]), .D(n4275), 
         .Z(n4245)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i1_4_lut_adj_35.init = 16'hc8c0;
    LUT4 i1_4_lut_adj_36 (.A(n288), .B(cnt[14]), .C(cnt[15]), .D(cnt[16]), 
         .Z(n226)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam i1_4_lut_adj_36.init = 16'hfffe;
    LUT4 i1_4_lut_adj_37 (.A(cnt[12]), .B(n215), .C(cnt[13]), .D(cnt[11]), 
         .Z(n212)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i1_4_lut_adj_37.init = 16'ha088;
    LUT4 i1_2_lut (.A(cnt[21]), .B(cnt[22]), .Z(n4243)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut.init = 16'h8888;
    LUT4 i256_4_lut (.A(cnt[11]), .B(cnt[13]), .C(n4), .D(cnt[12]), 
         .Z(n288)) /* synthesis lut_function=(A (B (D))+!A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i256_4_lut.init = 16'hc800;
    LUT4 i1_4_lut_adj_38 (.A(n3436), .B(n4226), .C(cnt[19]), .D(n4284), 
         .Z(n4227)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i1_4_lut_adj_38.init = 16'hc8c0;
    LUT4 i2499_4_lut (.A(n4253), .B(n4610), .C(cnt[22]), .D(cnt[21]), 
         .Z(n3611)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2499_4_lut.init = 16'hfcec;
    LUT4 i1_4_lut_adj_39 (.A(n208), .B(n4299), .C(n4246), .D(cnt[10]), 
         .Z(n3436)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut_adj_39.init = 16'hfcec;
    LUT4 i1_2_lut_adj_40 (.A(cnt[9]), .B(cnt[8]), .Z(n208)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i1_2_lut_adj_40.init = 16'h8888;
    LUT4 i1_4_lut_adj_41 (.A(n27), .B(n4226), .C(cnt[19]), .D(n4284), 
         .Z(n4228)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i1_4_lut_adj_41.init = 16'hc8c0;
    LUT4 i1_4_lut_adj_42 (.A(n20), .B(n4299), .C(n4246), .D(cnt[10]), 
         .Z(n27)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut_adj_42.init = 16'hfcec;
    LUT4 i656_4_lut (.A(cnt[8]), .B(cnt[9]), .C(cnt[7]), .D(n3113), 
         .Z(n20)) /* synthesis lut_function=(A (B)+!A (B (C (D)))) */ ;
    defparam i656_4_lut.init = 16'hc888;
    LUT4 i1_rep_6_3_lut (.A(cnt[14]), .B(cnt[15]), .C(cnt[16]), .Z(n4397)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam i1_rep_6_3_lut.init = 16'hfefe;
    CCU2D cnt_378_add_4_33 (.A0(cnt[31]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3841), .S0(n133[31]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_33.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_33.INIT1 = 16'h0000;
    defparam cnt_378_add_4_33.INJECT1_0 = "NO";
    defparam cnt_378_add_4_33.INJECT1_1 = "NO";
    LUT4 i1_4_lut_adj_43 (.A(cnt[10]), .B(n262), .C(cnt[13]), .D(cnt[9]), 
         .Z(n215)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i1_4_lut_adj_43.init = 16'ha088;
    LUT4 i1_2_lut_adj_44 (.A(cnt[11]), .B(cnt[12]), .Z(n4246)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_44.init = 16'h8888;
    LUT4 i1_2_lut_adj_45 (.A(cnt[20]), .B(cnt[21]), .Z(n4226)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_45.init = 16'h8888;
    LUT4 i1_4_lut_adj_46 (.A(n3914), .B(n4252), .C(cnt[18]), .D(n4281), 
         .Z(n4254)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i1_4_lut_adj_46.init = 16'hc8c0;
    CCU2D cnt_378_add_4_31 (.A0(cnt[29]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[30]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3840), .COUT(n3841), .S0(n133[29]), .S1(n133[30]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_31.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_31.INIT1 = 16'hfaaa;
    defparam cnt_378_add_4_31.INJECT1_0 = "NO";
    defparam cnt_378_add_4_31.INJECT1_1 = "NO";
    LUT4 i3142_4_lut (.A(led_status[0]), .B(n3877), .C(cnt[25]), .D(cnt[24]), 
         .Z(n4318)) /* synthesis lut_function=(A+(B (C)+!B (C (D)))) */ ;
    defparam i3142_4_lut.init = 16'hfaea;
    LUT4 i1_4_lut_adj_47 (.A(cnt[9]), .B(n4290), .C(n4255), .D(n201), 
         .Z(n3914)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam i1_4_lut_adj_47.init = 16'hfcec;
    CCU2D cnt_378_add_4_29 (.A0(cnt[27]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[28]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3839), .COUT(n3840), .S0(n133[27]), .S1(n133[28]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_29.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_29.INIT1 = 16'hfaaa;
    defparam cnt_378_add_4_29.INJECT1_0 = "NO";
    defparam cnt_378_add_4_29.INJECT1_1 = "NO";
    LUT4 i1_rep_9_2_lut (.A(cnt[15]), .B(cnt[16]), .Z(n4400)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam i1_rep_9_2_lut.init = 16'heeee;
    LUT4 i1_2_lut_adj_48 (.A(cnt[11]), .B(cnt[10]), .Z(n4255)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i1_2_lut_adj_48.init = 16'h8888;
    LUT4 i1_2_lut_adj_49 (.A(cnt[20]), .B(cnt[19]), .Z(n4252)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_49.init = 16'h8888;
    LUT4 i1_4_lut_adj_50 (.A(cnt[11]), .B(n262), .C(cnt[13]), .D(n4636), 
         .Z(n4_adj_1040)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;
    defparam i1_4_lut_adj_50.init = 16'ha088;
    LUT4 i3213_3_lut (.A(led_status[1]), .B(led_status[2]), .C(led_status[0]), 
         .Z(clk_c_enable_11)) /* synthesis lut_function=(!(A (B (C)))) */ ;
    defparam i3213_3_lut.init = 16'h7f7f;
    LUT4 i3164_4_lut (.A(cnt[26]), .B(cnt[31]), .C(cnt[30]), .D(cnt[28]), 
         .Z(n4340)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i3164_4_lut.init = 16'hfffe;
    LUT4 i2_4_lut_adj_51 (.A(cnt[23]), .B(cnt[22]), .C(n4233), .D(cnt[21]), 
         .Z(n3877)) /* synthesis lut_function=(A (B (C+(D)))) */ ;
    defparam i2_4_lut_adj_51.init = 16'h8880;
    LUT4 n4288_bdd_4_lut (.A(n3625), .B(n3621), .C(led_status[0]), .D(led_status[1]), 
         .Z(n4561)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)+!C !(D))+!B !(C+(D)))) */ ;
    defparam n4288_bdd_4_lut.init = 16'hca0f;
    LUT4 i12_3_lut (.A(led_status[1]), .B(led_status[0]), .C(led_status[2]), 
         .Z(clk_c_enable_87)) /* synthesis lut_function=(!(A (B (C))+!A !(C))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(53[9] 77[16])
    defparam i12_3_lut.init = 16'h7a7a;
    LUT4 i1_2_lut_adj_52 (.A(cnt[9]), .B(cnt[10]), .Z(n4)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i1_2_lut_adj_52.init = 16'h8888;
    CCU2D cnt_378_add_4_27 (.A0(cnt[25]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[26]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3838), .COUT(n3839), .S0(n133[25]), .S1(n133[26]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_27.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_27.INIT1 = 16'hfaaa;
    defparam cnt_378_add_4_27.INJECT1_0 = "NO";
    defparam cnt_378_add_4_27.INJECT1_1 = "NO";
    LUT4 i1_4_lut_adj_53 (.A(cnt[9]), .B(cnt[13]), .C(n4_adj_1040), .D(n14), 
         .Z(n11)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_53.init = 16'heca0;
    LUT4 i1_2_lut_adj_54 (.A(cnt[11]), .B(cnt[12]), .Z(n4302)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i1_2_lut_adj_54.init = 16'heeee;
    LUT4 i1_4_lut_adj_55 (.A(n3916), .B(n4252), .C(cnt[18]), .D(n4281), 
         .Z(n4253)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i1_4_lut_adj_55.init = 16'hc8c0;
    CCU2D cnt_378_add_4_25 (.A0(cnt[23]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[24]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3837), .COUT(n3838), .S0(n133[23]), .S1(n133[24]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_25.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_25.INIT1 = 16'hfaaa;
    defparam cnt_378_add_4_25.INJECT1_0 = "NO";
    defparam cnt_378_add_4_25.INJECT1_1 = "NO";
    CCU2D cnt_378_add_4_23 (.A0(cnt[21]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[22]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3836), .COUT(n3837), .S0(n133[21]), .S1(n133[22]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_23.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_23.INIT1 = 16'hfaaa;
    defparam cnt_378_add_4_23.INJECT1_0 = "NO";
    defparam cnt_378_add_4_23.INJECT1_1 = "NO";
    CCU2D cnt_378_add_4_21 (.A0(cnt[19]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[20]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3835), .COUT(n3836), .S0(n133[19]), .S1(n133[20]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_21.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_21.INIT1 = 16'hfaaa;
    defparam cnt_378_add_4_21.INJECT1_0 = "NO";
    defparam cnt_378_add_4_21.INJECT1_1 = "NO";
    LUT4 i1_4_lut_adj_56 (.A(cnt[9]), .B(n4290), .C(n4255), .D(n4639), 
         .Z(n3916)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i1_4_lut_adj_56.init = 16'hfcec;
    LUT4 i1_4_lut_adj_57 (.A(cnt[17]), .B(n4638), .C(n5_adj_1041), .D(n6), 
         .Z(n4231)) /* synthesis lut_function=(A (B)+!A (B (C (D)))) */ ;
    defparam i1_4_lut_adj_57.init = 16'hc888;
    LUT4 i1_4_lut_adj_58 (.A(n4302), .B(cnt[14]), .C(n4260), .D(cnt[13]), 
         .Z(n5_adj_1041)) /* synthesis lut_function=(A (B)+!A (B (C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam i1_4_lut_adj_58.init = 16'hccc8;
    CCU2D cnt_378_add_4_19 (.A0(cnt[17]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[18]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3834), .COUT(n3835), .S0(n133[17]), .S1(n133[18]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_19.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_19.INIT1 = 16'hfaaa;
    defparam cnt_378_add_4_19.INJECT1_0 = "NO";
    defparam cnt_378_add_4_19.INJECT1_1 = "NO";
    CCU2D cnt_378_add_4_17 (.A0(cnt[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3833), .COUT(n3834), .S0(n133[15]), .S1(n133[16]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_17.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_17.INIT1 = 16'hfaaa;
    defparam cnt_378_add_4_17.INJECT1_0 = "NO";
    defparam cnt_378_add_4_17.INJECT1_1 = "NO";
    LUT4 i2_2_lut (.A(cnt[15]), .B(cnt[16]), .Z(n6)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam i2_2_lut.init = 16'h8888;
    CCU2D cnt_378_add_4_15 (.A0(cnt[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3832), .COUT(n3833), .S0(n133[13]), .S1(n133[14]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_15.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_15.INIT1 = 16'hfaaa;
    defparam cnt_378_add_4_15.INJECT1_0 = "NO";
    defparam cnt_378_add_4_15.INJECT1_1 = "NO";
    CCU2D cnt_378_add_4_13 (.A0(cnt[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3831), .COUT(n3832), .S0(n133[11]), .S1(n133[12]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_13.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_13.INIT1 = 16'hfaaa;
    defparam cnt_378_add_4_13.INJECT1_0 = "NO";
    defparam cnt_378_add_4_13.INJECT1_1 = "NO";
    PFUMX i3247 (.BLUT(n4559), .ALUT(n4558), .C0(led_status[1]), .Z(n4560));
    CCU2D cnt_378_add_4_11 (.A0(cnt[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3830), 
          .COUT(n3831), .S0(n133[9]), .S1(n133[10]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_11.INIT1 = 16'hfaaa;
    defparam cnt_378_add_4_11.INJECT1_0 = "NO";
    defparam cnt_378_add_4_11.INJECT1_1 = "NO";
    CCU2D cnt_378_add_4_9 (.A0(cnt[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3829), 
          .COUT(n3830), .S0(n133[7]), .S1(n133[8]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_378_add_4_9.INJECT1_0 = "NO";
    defparam cnt_378_add_4_9.INJECT1_1 = "NO";
    CCU2D cnt_378_add_4_7 (.A0(cnt[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3828), 
          .COUT(n3829), .S0(n133[5]), .S1(n133[6]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_378_add_4_7.INJECT1_0 = "NO";
    defparam cnt_378_add_4_7.INJECT1_1 = "NO";
    CCU2D cnt_378_add_4_5 (.A0(cnt[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3827), 
          .COUT(n3828), .S0(n133[3]), .S1(n133[4]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_378_add_4_5.INJECT1_0 = "NO";
    defparam cnt_378_add_4_5.INJECT1_1 = "NO";
    CCU2D cnt_378_add_4_3 (.A0(cnt[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3826), 
          .COUT(n3827), .S0(n133[1]), .S1(n133[2]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_378_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_378_add_4_3.INJECT1_0 = "NO";
    defparam cnt_378_add_4_3.INJECT1_1 = "NO";
    CCU2D cnt_378_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n3826), 
          .S1(n133[0]));   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(73[56:66])
    defparam cnt_378_add_4_1.INIT0 = 16'hF000;
    defparam cnt_378_add_4_1.INIT1 = 16'h0555;
    defparam cnt_378_add_4_1.INJECT1_0 = "NO";
    defparam cnt_378_add_4_1.INJECT1_1 = "NO";
    LUT4 i1_4_lut_adj_59 (.A(cnt[8]), .B(n4), .C(cnt[7]), .D(cnt[6]), 
         .Z(n4260)) /* synthesis lut_function=(A (B)+!A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i1_4_lut_adj_59.init = 16'hc888;
    LUT4 i1_4_lut_adj_60 (.A(n3915), .B(cnt[18]), .C(cnt[16]), .D(cnt[17]), 
         .Z(n4_adj_1037)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B+(D))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i1_4_lut_adj_60.init = 16'hffec;
    LUT4 i1738_4_lut (.A(n2476), .B(cnt[19]), .C(cnt[20]), .D(n4_adj_1038), 
         .Z(n3593)) /* synthesis lut_function=(A (B+((D)+!C))+!A (B (C)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/h_brige/ledstatus.v(46[16:19])
    defparam i1738_4_lut.init = 16'hfaca;
    
endmodule
